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      1 /*	$NetBSD: p5pb.c,v 1.12 2012/10/27 17:17:34 chs Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Radoslaw Kujawa.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/types.h>
     33 #include <sys/param.h>
     34 #include <sys/time.h>
     35 #include <sys/systm.h>
     36 #include <sys/errno.h>
     37 #include <sys/device.h>
     38 #include <sys/malloc.h>
     39 #include <sys/kmem.h>
     40 #include <sys/extent.h>
     41 
     42 #include <uvm/uvm_extern.h>
     43 
     44 #define _M68K_BUS_DMA_PRIVATE
     45 #include <machine/bus.h>
     46 #include <machine/cpu.h>
     47 
     48 #include <m68k/bus_dma.h>
     49 #include <amiga/dev/zbusvar.h>
     50 #include <amiga/dev/p5busvar.h>
     51 #include <amiga/pci/p5pbreg.h>
     52 #include <amiga/pci/p5pbvar.h>
     53 #include <amiga/pci/p5membarvar.h>
     54 
     55 #include <dev/pci/pcivar.h>
     56 #include <dev/pci/pcireg.h>
     57 #include <dev/pci/pcidevs.h>
     58 #ifdef PCI_NETBSD_CONFIGURE
     59 #include <dev/pci/pciconf.h>
     60 #endif /* PCI_NETBSD_CONFIGURE */
     61 
     62 #include "opt_p5pb.h"
     63 #include "opt_pci.h"
     64 
     65 /* Initial CVPPC/BVPPC resolution as configured by the firmware */
     66 #define P5GFX_WIDTH		640
     67 #define P5GFX_HEIGHT		480
     68 #define P5GFX_DEPTH		8
     69 #define P5GFX_LINEBYTES		640
     70 
     71 struct m68k_bus_dma_tag p5pb_bus_dma_tag = {
     72 	0,
     73 	0,
     74 	_bus_dmamap_create,
     75 	_bus_dmamap_destroy,
     76 	_bus_dmamap_load_direct,
     77 	_bus_dmamap_load_mbuf_direct,
     78 	_bus_dmamap_load_uio_direct,
     79 	_bus_dmamap_load_raw_direct,
     80 	_bus_dmamap_unload,
     81 	_bus_dmamap_sync,
     82 	_bus_dmamem_alloc,
     83 	_bus_dmamem_free,
     84 	_bus_dmamem_map,
     85 	_bus_dmamem_unmap,
     86 	_bus_dmamem_mmap
     87 };
     88 
     89 static int	p5pb_match(device_t, cfdata_t, void *);
     90 static void	p5pb_attach(device_t, device_t, void *);
     91 void		p5pb_set_props(struct p5pb_softc *);
     92 pcireg_t	p5pb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int);
     93 void		p5pb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
     94 int		p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t, int);
     95 int		p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t, int);
     96 int		p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t, int);
     97 int		p5pb_pci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t);
     98 void		p5pb_pci_attach_hook (device_t, device_t,
     99 		    struct pcibus_attach_args *);
    100 pcitag_t	p5pb_pci_make_tag(pci_chipset_tag_t, int, int, int);
    101 void		p5pb_pci_decompose_tag(pci_chipset_tag_t, pcitag_t,
    102 		    int *, int *, int *);
    103 int		p5pb_pci_intr_map(const struct pci_attach_args *,
    104 		    pci_intr_handle_t *);
    105 bool		p5pb_bus_map_memio(struct p5pb_softc *);
    106 bool		p5pb_bus_map_conf(struct p5pb_softc *);
    107 uint8_t		p5pb_find_resources(struct p5pb_softc *);
    108 static bool	p5pb_identify_bridge(struct p5pb_softc *);
    109 void		p5pb_membar_grex(struct p5pb_softc *);
    110 static bool	p5pb_cvppc_probe(struct p5pb_softc *);
    111 #ifdef PCI_NETBSD_CONFIGURE
    112 bool		p5pb_bus_reconfigure(struct p5pb_softc *);
    113 #endif /* PCI_NETBSD_CONFIGURE */
    114 #ifdef P5PB_DEBUG
    115 void		p5pb_usable_ranges(struct p5pb_softc *);
    116 void		p5pb_badaddr_range(struct p5pb_softc *, bus_space_tag_t,
    117 		    bus_addr_t, size_t);
    118 void		p5pb_conf_search(struct p5pb_softc *, uint16_t);
    119 #endif /* P5PB_DEBUG */
    120 
    121 CFATTACH_DECL_NEW(p5pb, sizeof(struct p5pb_softc),
    122     p5pb_match, p5pb_attach, NULL, NULL);
    123 
    124 static int
    125 p5pb_match(device_t parent, cfdata_t cf, void *aux)
    126 {
    127 	struct p5bus_attach_args *p5baa;
    128 
    129 	p5baa = (struct p5bus_attach_args *) aux;
    130 
    131 	if (strcmp(p5baa->p5baa_name, "p5pb") == 0)
    132 		return 1;
    133 
    134 	return 0;
    135 }
    136 
    137 static void
    138 p5pb_attach(device_t parent, device_t self, void *aux)
    139 {
    140 	struct p5pb_softc *sc;
    141 	struct pcibus_attach_args pba;
    142 
    143 	sc = device_private(self);
    144 	sc->sc_dev = self;
    145 	sc->p5baa = (struct p5bus_attach_args *) aux;
    146 
    147 	pci_chipset_tag_t pc = &sc->apc;
    148 
    149 	if (!p5pb_bus_map_conf(sc)) {
    150 		aprint_error_dev(self,
    151 		    "couldn't map PCI configuration space\n");
    152 		return;
    153 	}
    154 
    155 	if (!p5pb_identify_bridge(sc)) {
    156 		return;
    157 	}
    158 
    159 	if (sc->bridge_type == P5PB_BRIDGE_CVPPC) {
    160 		sc->pci_mem_lowest = P5BUS_PCI_MEM_BASE;
    161 		sc->pci_mem_highest = P5BUS_PCI_MEM_BASE + P5BUS_PCI_MEM_SIZE;
    162 	} else {
    163 		p5pb_membar_grex(sc);
    164 	}
    165 
    166 	if (!p5pb_bus_map_memio(sc)) {
    167 		aprint_error_dev(self,
    168 		    "couldn't map PCI I/O and memory space\n");
    169 		return;
    170 	}
    171 
    172 #ifdef P5PB_DEBUG
    173 	aprint_normal("p5pb: map conf %x -> %x, io %x -> %x, mem %x -> %x\n",
    174 	    kvtop((void*) sc->pci_conf_area.base), sc->pci_conf_area.base,
    175 	    kvtop((void*) sc->pci_io_area.base), sc->pci_io_area.base,
    176 	    kvtop((void*) sc->pci_mem_area.base), sc->pci_mem_area.base );
    177 #endif
    178 
    179 	/* Initialize the PCI chipset tag. */
    180 
    181 	if (sc->bridge_type == P5PB_BRIDGE_GREX1200)
    182 		sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex1200;
    183 	else if (sc->bridge_type == P5PB_BRIDGE_GREX4000)
    184 		sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex4000;
    185 	else
    186 		sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_cvppc;
    187 
    188 	sc->apc.pc_conf_v = (void*) pc;
    189 	sc->apc.pc_make_tag = amiga_pci_make_tag;
    190 	sc->apc.pc_decompose_tag = amiga_pci_decompose_tag;
    191 	sc->apc.pc_conf_read = p5pb_pci_conf_read;
    192 	sc->apc.pc_conf_write = p5pb_pci_conf_write;
    193 	sc->apc.pc_conf_hook = p5pb_pci_conf_hook;
    194 	sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt;
    195 	sc->apc.pc_attach_hook = p5pb_pci_attach_hook;
    196 
    197 	sc->apc.pc_intr_map = p5pb_pci_intr_map;
    198 	sc->apc.pc_intr_string = amiga_pci_intr_string;
    199 	sc->apc.pc_intr_establish = amiga_pci_intr_establish;
    200 	sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish;
    201 
    202 #ifdef PCI_NETBSD_CONFIGURE
    203 	/* Never reconfigure the bus on CVPPC/BVPPC, avoid the fb breakage. */
    204 	if (sc->bridge_type != P5PB_BRIDGE_CVPPC) {
    205 		p5pb_bus_reconfigure(sc);
    206 	}
    207 #endif /* PCI_NETBSD_CONFIGURE */
    208 
    209 	/* Initialize the bus attachment structure. */
    210 
    211 	pba.pba_iot = &(sc->pci_io_area);
    212 	pba.pba_memt = &(sc->pci_mem_area);
    213 	pba.pba_dmat = &p5pb_bus_dma_tag;
    214 	pba.pba_dmat64 = NULL;
    215 	pba.pba_pc = pc;
    216 	pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
    217 	pba.pba_bus = 0;
    218 	pba.pba_bridgetag = NULL;
    219 
    220 	p5pb_set_props(sc);
    221 
    222 	config_found_ia(self, "pcibus", &pba, pcibusprint);
    223 }
    224 
    225 /*
    226  * Try to detect what kind of bridge are we dealing with.
    227  */
    228 static bool
    229 p5pb_identify_bridge(struct p5pb_softc *sc)
    230 {
    231 	int pcires_count;	/* Number of AutoConfig(TM) PCI resources */
    232 
    233 	pcires_count = p5pb_find_resources(sc);
    234 
    235 	switch (pcires_count) {
    236 	case 0:
    237 		/*
    238 		 * Zero AutoConfig(TM) PCI resources, means that there's nothing
    239 		 * OR there's a CVPPC/BVPPC with a pre-44.69 firmware.
    240 		 */
    241 		if (p5pb_cvppc_probe(sc)) {
    242 			sc->bridge_type = P5PB_BRIDGE_CVPPC;
    243 			aprint_normal(": Phase5 CVPPC/BVPPC PCI bridge\n");
    244 		} else {
    245 			aprint_normal(": no PCI bridges detected\n");
    246 			return false;
    247 		}
    248 		break;
    249 	case 6:
    250 		/*
    251 		 * We have a slight possibility, that there's a CVPPC/BVPPC with
    252 		 * the new firmware. So check for it first.
    253 		 */
    254 		if (p5pb_cvppc_probe(sc)) {
    255 			/* New firmware, treat as one-slot GREX. */
    256 			sc->bridge_type = P5PB_BRIDGE_CVPPC;
    257 			aprint_normal(
    258 			    ": Phase5 CVPPC/BVPPC PCI bridge (44.69/44.71)\n");
    259 			break;
    260 		}
    261 	default:
    262 		/* We have a G-REX surely. */
    263 
    264 		if (sc->p5baa->p5baa_cardtype == P5_CARDTYPE_CS) {
    265 			sc->bridge_type = P5PB_BRIDGE_GREX4000;
    266 			aprint_normal(": DCE G-REX 4000 PCI bridge\n");
    267 		} else {
    268 			sc->bridge_type = P5PB_BRIDGE_GREX1200;
    269 			aprint_normal(": DCE G-REX 1200 PCI bridge\n");
    270 		}
    271 		break;
    272 	}
    273 	return true;
    274 }
    275 
    276 /*
    277  * Find AutoConfig(TM) resuorces (for boards running G-REX firmware). Return the
    278  * total number of found resources.
    279  */
    280 uint8_t
    281 p5pb_find_resources(struct p5pb_softc *sc)
    282 {
    283 	uint8_t i, rv;
    284 	struct p5pb_autoconf_entry *auto_entry;
    285 	struct p5membar_softc *membar_sc;
    286 	device_t p5membar_dev;
    287 
    288 	rv = 0;
    289 
    290 	TAILQ_INIT(&sc->auto_bars);
    291 
    292 	/* 255 should be enough for everybody */
    293 	for(i = 0; i < 255; i++) {
    294 
    295 		if ((p5membar_dev =
    296 		    device_find_by_driver_unit("p5membar", i)) != NULL) {
    297 
    298 			rv++;
    299 
    300 			membar_sc = device_private(p5membar_dev);
    301 			if (membar_sc->sc_type == P5MEMBAR_TYPE_INTERNAL)
    302 				continue;
    303 
    304 			auto_entry =
    305 			    kmem_alloc(sizeof(struct p5pb_autoconf_entry),
    306 			    KM_SLEEP);
    307 
    308 			auto_entry->base = membar_sc->sc_base;
    309 			auto_entry->size = membar_sc->sc_size;
    310 
    311 			TAILQ_INSERT_TAIL(&sc->auto_bars, auto_entry, entries);
    312 		}
    313 	}
    314 	return rv;
    315 }
    316 
    317 /*
    318  * Set properties needed to support fb driver. These are read later during
    319  * autoconfg in device_register(). Needed for CVPPC/BVPPC.
    320  */
    321 void
    322 p5pb_set_props(struct p5pb_softc *sc)
    323 {
    324 #if NGENFB > 0
    325 	prop_dictionary_t dict;
    326 	device_t dev;
    327 
    328 	dev = sc->sc_dev;
    329 	dict = device_properties(dev);
    330 
    331 	/* genfb needs additional properties, like virtual, physical address */
    332 	/* XXX: currently genfb is supported only on CVPPC/BVPPC */
    333 	prop_dictionary_set_uint64(dict, "virtual_address",
    334 	    sc->pci_mem_area.base);
    335 	prop_dictionary_set_uint64(dict, "address",
    336 	    kvtop((void*) sc->pci_mem_area.base));
    337 #endif
    338 }
    339 
    340 pcireg_t
    341 p5pb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
    342 {
    343 	uint32_t data;
    344 	uint32_t bus, dev, func;
    345 	uint32_t offset;
    346 
    347 	pci_decompose_tag(pc, tag, &bus, &dev, &func);
    348 
    349 	offset = (OFF_PCI_DEVICE << dev) + reg;
    350 
    351 	if(func == 0)	/* ugly, ugly hack */
    352 		offset += 0;
    353 	else if(func == 1)
    354 		offset += OFF_PCI_FUNCTION;
    355 	else
    356 		return 0xFFFFFFFF;
    357 
    358 	if(badaddr((void *)__UNVOLATILE(((uint32_t)
    359 	    bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah)
    360 	    + offset))))
    361 		return 0xFFFFFFFF;
    362 
    363 	data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah,
    364 	    offset);
    365 #ifdef P5PB_DEBUG_CONF
    366 	aprint_normal("p5pb conf read va: %lx, bus: %d, dev: %d, "
    367 	    "func: %d, reg: %d -r-> data %x\n",
    368 	    pc->pci_conf_datah, bus, dev, func, reg, data);
    369 #endif
    370 	return data;
    371 }
    372 
    373 void
    374 p5pb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)
    375 {
    376 	uint32_t bus, dev, func;
    377 	uint32_t offset;
    378 
    379 	pci_decompose_tag(pc, tag, &bus, &dev, &func);
    380 
    381 	offset = (OFF_PCI_DEVICE << dev) + reg;
    382 
    383 	if(func == 0)	/* ugly, ugly hack */
    384 		offset += 0;
    385 	else if(func == 1)
    386 		offset += OFF_PCI_FUNCTION;
    387 	else
    388 		return;
    389 
    390 	if(badaddr((void *)__UNVOLATILE(((uint32_t)
    391 	    bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah)
    392 	    + offset))))
    393 		return;
    394 
    395 	bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah,
    396 	    offset, val);
    397 #ifdef P5PB_DEBUG_CONF
    398 	aprint_normal("p5pb conf write va: %lx, bus: %d, dev: %d, "
    399 	    "func: %d, reg: %d -w-> data %x\n",
    400 	    pc->pci_conf_datah, bus, dev, func, reg, val);
    401 #endif
    402 
    403 }
    404 
    405 int
    406 p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t pc, int busno)
    407 {
    408 	/* CVPPC/BVPPC has only 1 "slot". */
    409 	return 1;
    410 }
    411 
    412 int
    413 p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t pc, int busno)
    414 {
    415 	/* G-REX 4000 has 4, G-REX 4000T has 3 slots? */
    416 	return 4;
    417 }
    418 
    419 int
    420 p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t pc, int busno)
    421 {
    422 	/* G-REX 1200 has 5 slots. */
    423 	return 4; /* XXX: 5 not yet! */
    424 }
    425 
    426 void
    427 p5pb_pci_attach_hook(device_t parent, device_t self,
    428     struct pcibus_attach_args *pba)
    429 {
    430 }
    431 
    432 int
    433 p5pb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
    434 {
    435 	/* TODO: add sanity checking */
    436 
    437 	*ihp = 2;
    438 	return 0;
    439 }
    440 
    441 /* Probe for CVPPC/BVPPC. */
    442 static bool
    443 p5pb_cvppc_probe(struct p5pb_softc *sc)
    444 {
    445 	bus_space_handle_t probe_h;
    446 	uint16_t prodid, manid;
    447 	void* data;
    448 	bool rv;
    449 
    450 	manid = 0; prodid = 0;
    451 	rv = false;
    452 
    453 	if (bus_space_map(sc->apc.pci_conf_datat, 0, 4, 0, &probe_h))
    454 		return rv;
    455 
    456 	data = bus_space_vaddr(sc->apc.pci_conf_datat, probe_h);
    457 
    458 	if (badaddr((void *)__UNVOLATILE((uint32_t) data))) {
    459 #ifdef P5PB_DEBUG_PROBE
    460 		aprint_normal("p5pb: CVPPC configuration space not usable!\n");
    461 #endif /* P5PB_DEBUG_PROBE */
    462 	} else {
    463 		prodid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 0);
    464 		manid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 2);
    465 
    466 		if ((prodid == P5PB_PM2_PRODUCT_ID) &&
    467 		    (manid == P5PB_PM2_VENDOR_ID))
    468 			rv = true;
    469 	}
    470 
    471 #ifdef P5PB_DEBUG_PROBE
    472 	aprint_normal("p5pb: CVPPC probe for PCI ID: %x, %x returns %d\n",
    473 	    manid, prodid, (int) rv);
    474 #endif /* P5PB_DEBUG_PROBE */
    475 
    476 	bus_space_unmap(sc->apc.pci_conf_datat, probe_h, 4);
    477 	return rv;
    478 }
    479 
    480 #ifdef PCI_NETBSD_CONFIGURE
    481 /* Reconfigure the bus. */
    482 bool
    483 p5pb_bus_reconfigure(struct p5pb_softc *sc)
    484 {
    485 	struct extent		*ioext, *memext;
    486 	pci_chipset_tag_t	pc;
    487 
    488 	pc = &sc->apc;
    489 
    490 	ioext = extent_create("p5pbio", 0, P5BUS_PCI_IO_SIZE, NULL, 0,
    491 	    EX_NOWAIT);
    492 
    493 	memext = extent_create("p5pbmem", sc->pci_mem_lowest,
    494 	     sc->pci_mem_highest - 1, NULL, 0, EX_NOWAIT);
    495 
    496 	if ( (!ioext) || (!memext) )
    497 		return false;
    498 
    499 #ifdef P5PB_DEBUG
    500 	aprint_normal("p5pb: reconfiguring the bus!\n");
    501 #endif /* P5PB_DEBUG */
    502 	pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);
    503 
    504 	extent_destroy(ioext);
    505 	extent_destroy(memext);
    506 
    507 	return true; /* TODO: better error handling */
    508 }
    509 #endif /* PCI_NETBSD_CONFIGURE */
    510 
    511 /* Determine the PCI memory space (done G-REX-style). */
    512 void
    513 p5pb_membar_grex(struct p5pb_softc *sc)
    514 {
    515 	struct p5pb_autoconf_entry *membar_entry;
    516 	uint32_t bar_address;
    517 
    518 	sc->pci_mem_lowest = 0xFFFFFFFF;
    519 	sc->pci_mem_highest = 0;
    520 
    521 	/* Iterate over membar entries to find lowest and highest address. */
    522 	TAILQ_FOREACH(membar_entry, &sc->auto_bars, entries) {
    523 
    524 		bar_address = (uint32_t) membar_entry->base;
    525 		if ((bar_address + membar_entry->size) > sc->pci_mem_highest)
    526 			sc->pci_mem_highest = bar_address + membar_entry->size;
    527 		if (bar_address < sc->pci_mem_lowest)
    528 			sc->pci_mem_lowest = bar_address;
    529 
    530 #ifdef P5PB_DEBUG_BAR
    531 		aprint_normal("p5pb: %d kB mem BAR at %p, hi = %x, lo = %x\n",
    532 		    membar_entry->size / 1024, membar_entry->base,
    533 		    sc->pci_mem_highest, sc->pci_mem_lowest);
    534 #endif /* P5PB_DEBUG_BAR */
    535 	}
    536 
    537 	aprint_normal("p5pb: %d kB PCI memory space (%8p to %8p)\n",
    538 	    (sc->pci_mem_highest - sc->pci_mem_lowest) / 1024,
    539 	     (void*) sc->pci_mem_lowest, (void*) sc->pci_mem_highest);
    540 
    541 }
    542 
    543 bool
    544 p5pb_bus_map_conf(struct p5pb_softc *sc)
    545 {
    546 	sc->pci_conf_area.base = (bus_addr_t) zbusmap(
    547 	    (void *) P5BUS_PCI_CONF_BASE, P5BUS_PCI_CONF_SIZE);
    548 	sc->pci_conf_area.absm = &amiga_bus_stride_1;
    549 
    550 	sc->apc.pci_conf_datat = &(sc->pci_conf_area);
    551 
    552 	if (bus_space_map(sc->apc.pci_conf_datat, OFF_PCI_CONF_DATA,
    553 	    P5BUS_PCI_CONF_SIZE, 0, &sc->apc.pci_conf_datah))
    554 		return false;
    555 
    556 	return true;
    557 }
    558 
    559 /* Map I/O and memory space. */
    560 bool
    561 p5pb_bus_map_memio(struct p5pb_softc *sc)
    562 {
    563 	sc->pci_io_area.base = (bus_addr_t) zbusmap(
    564 	    (void *) P5BUS_PCI_IO_BASE, P5BUS_PCI_IO_SIZE);
    565 	sc->pci_io_area.absm = &amiga_bus_stride_1swap;
    566 
    567 	sc->pci_mem_area.base = (bus_addr_t) zbusmap(
    568 	    (void *) sc->pci_mem_lowest,
    569 	    sc->pci_mem_highest - sc->pci_mem_lowest);
    570 	sc->pci_mem_area.absm = &amiga_bus_stride_1swap_abs;
    571 
    572 	return true;
    573 }
    574 
    575 int
    576 p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev,
    577     int func, pcireg_t id)
    578 {
    579 	/* XXX: What should we do on CVPPC/BVPPC? It breaks genfb. */
    580 
    581 	return PCI_CONF_DEFAULT;
    582 }
    583 
    584 #ifdef P5PB_DEBUG
    585 /* Check which config and I/O ranges are usable. */
    586 void
    587 p5pb_usable_ranges(struct p5pb_softc *sc)
    588 {
    589 	p5pb_badaddr_range(sc, &(sc->pci_conf_area), 0, P5BUS_PCI_CONF_SIZE);
    590 	p5pb_badaddr_range(sc, &(sc->pci_io_area), 0, P5BUS_PCI_IO_SIZE);
    591 }
    592 
    593 void
    594 p5pb_badaddr_range(struct p5pb_softc *sc, bus_space_tag_t bust, bus_addr_t base,
    595     size_t len)
    596 {
    597 	int i, state, prev_state;
    598 	bus_space_handle_t bush;
    599 	volatile void *data;
    600 
    601 	state = -1;
    602 	prev_state = -1;
    603 
    604 	bus_space_map(bust, base, len, 0, &bush);
    605 
    606 	aprint_normal("p5pb: badaddr range check from %x (%x) to %x (%x)\n",
    607 	    (bus_addr_t) bush,			/* start VA */
    608 	    (bus_addr_t) kvtop((void*) bush),	/* start PA */
    609 	    (bus_addr_t) bush + len,		/* end VA */
    610 	    (bus_addr_t) kvtop((void*) (bush + len)));/* end PA */
    611 
    612 	data = bus_space_vaddr(bust, bush);
    613 
    614 	for(i = 0; i < len; i++) {
    615 		state = badaddr((void *)__UNVOLATILE(((uint32_t) data + i)));
    616 		if(state != prev_state) {
    617 			aprint_normal("p5pb: badaddr %p (%x) : %d\n",
    618 			    (void*) ((uint32_t) data + i),
    619 			    (bus_addr_t) kvtop((void*) ((uint32_t) data + i)),
    620 			    state);
    621 			prev_state = state;
    622 		}
    623 
    624 	}
    625 
    626 	bus_space_unmap(bust, bush, len);
    627 }
    628 
    629 /* Search for 16-bit value in the configuration space. */
    630 void
    631 p5pb_conf_search(struct p5pb_softc *sc, uint16_t val)
    632 {
    633 	int i, state;
    634 	uint16_t readv;
    635 	void *va;
    636 
    637 	va = bus_space_vaddr(sc->apc.pci_conf_datat, sc->apc.pci_conf_datah);
    638 
    639 	for (i = 0; i < P5BUS_PCI_CONF_SIZE; i++) {
    640 		state = badaddr((void *)__UNVOLATILE(((uint32_t) va + i)));
    641 		if(state == 0) {
    642 			readv = bus_space_read_2(sc->apc.pci_conf_datat,
    643 			    sc->apc.pci_conf_datah, i);
    644 			if(readv == val)
    645 				aprint_normal("p5pb: found val %x @ %x (%x)\n",
    646 				    readv, (uint32_t) sc->apc.pci_conf_datah
    647 				    + i, (bus_addr_t) kvtop((void*)
    648 				    ((uint32_t) sc->apc.pci_conf_datah + i)));
    649 		}
    650 	}
    651 }
    652 
    653 #endif /* P5PB_DEBUG */
    654 
    655 #ifdef P5PB_CONSOLE
    656 void
    657 p5pb_device_register(device_t dev, void *aux)
    658 {
    659 	prop_dictionary_t dict, parent_dict;
    660 	struct pci_attach_args *pa = aux;
    661 
    662 	if (device_parent(dev) && device_is_a(device_parent(dev), "pci")) {
    663 
    664 		dict = device_properties(dev);
    665 
    666 		if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) {
    667 
    668 			/* Handle the CVPPC/BVPPC card... */
    669 			if ( ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TI)
    670 			    && (PCI_PRODUCT(pa->pa_id) ==
    671 			    PCI_PRODUCT_TI_TVP4020) ) ||
    672 			    /* ...and 3Dfx Voodoo 3 in G-REX. */
    673 			    ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX)
    674 			    && (PCI_PRODUCT(pa->pa_id) ==
    675 			    PCI_PRODUCT_3DFX_VOODOO3) )) {
    676 
    677 				parent_dict = device_properties(
    678 				    device_parent(device_parent(dev)));
    679 
    680 				prop_dictionary_set_uint32(dict, "width",
    681 				    P5GFX_WIDTH);
    682 
    683 				prop_dictionary_set_uint32(dict, "height",
    684 				    P5GFX_HEIGHT);
    685 
    686 				prop_dictionary_set_uint32(dict, "depth",
    687 				    P5GFX_DEPTH);
    688 
    689 #if (NGENFB > 0)
    690 				prop_dictionary_set_uint32(dict, "linebytes",
    691 				    P5GFX_LINEBYTES);
    692 
    693 				prop_dictionary_set(dict, "address",
    694 				    prop_dictionary_get(parent_dict,
    695 				    "address"));
    696 				prop_dictionary_set(dict, "virtual_address",
    697 				    prop_dictionary_get(parent_dict,
    698 				    "virtual_address"));
    699 #endif
    700 				prop_dictionary_set_bool(dict, "is_console",
    701 				    true);
    702                         }
    703                 }
    704         }
    705 }
    706 #endif /* P5PB_CONSOLE */
    707