Cross Reference: /src/sys/arch/arm/nvidia/tegra

Lines Matching +defs:error +defs:range
221 	int error, n;
239 	error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh);
240 	if (error) {
241 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
251 	error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci);
252 	if (error) {
253 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
262 	error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs);
263 	if (error) {
264 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
314 	error = clk_enable(clk); /* XXX set frequency */
315 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
316 	tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock");
320 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
321 	error = clk_set_rate(clk, 102000000);
322 	tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate");
325 	error = clk_enable(clk); /* XXX set frequency */
326 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
327 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock");
331 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
332 	error = clk_set_rate(clk, 204000000);
333 	tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate");
336 	error = clk_enable(clk);
337 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
338 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock");
342 	error = clk_enable(clk); /* XXX set frequency */
343 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
347 	error = clk_enable(clk); /* XXX set frequency */
348 	DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error);
349 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock");
358 		error = clk_set_rate(psc->sc_clk_ss_src, 2000000);
360 		DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error);
361 		tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate");
365 		tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate");
367 		error = clk_set_rate(psc->sc_clk_ss_src, 120000000);
369 		DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
370 		tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate");
374 	error = clk_enable(psc->sc_clk_ss_src);
375 	DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
376 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock");
380 	error = 0;
382 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
387 	error = clk_enable(clk); /* XXX set frequency */
388 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
389 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock");
432 	int error;
447 	error = clk_enable(clk);
448 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
452 	error = clk_enable(clk);
453 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
492 	error = xhci_init(sc);
493 	if (error) {
494 		aprint_error_dev(self, "init failed, error=%d\n", error);
505 	error = xusb_mailbox_send(psc, 0x01000000);
506 	if (error) {
507 		aprint_error_dev(self, "send failed, error=%d\n", error);
521 	int error;
558 			error = clk_set_rate(psc->sc_clk_ss_src, data * 1000);
559 			if (error != 0)
606 	int n, error;
617 		error = fdtbus_regulator_enable(reg);
618 		if (error != 0)
620 			    psc->sc_txd->txd_supplies[n], error);
745 	int error;
771 		error = firmware_open(fw_path, "xusb.bin", &fw);
772 		if (error != 0) {
775 			    fw_path, error);
776 			return error;
781 	error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE,
783 	if (error != 0)
784 		return error;
788 		error = firmware_read(fw, 0, firmware_image, firmware_size);
789 		if (error != 0) {
792 			return error;
923 	const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE);
928 	bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range);
936 	const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE);
941 	bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range);