Lines Matching defs:tmp_r
314 uint32_t tmp_r;
324 tmp_r = REG_RD(PWR_VDDIOCTRL);
325 tmp_r &= ~HW_POWER_VDDIOCTRL_LINREG_OFFSET;
326 tmp_r |= __SHIFTIN(2, HW_POWER_VDDIOCTRL_LINREG_OFFSET);
327 REG_WR(PWR_VDDIOCTRL, tmp_r);
331 tmp_r = REG_RD(PWR_VDDIOCTRL);
332 tmp_r &= ~HW_POWER_VDDIOCTRL_DISABLE_FET;
333 REG_WR(PWR_VDDIOCTRL, tmp_r);
337 tmp_r = REG_RD(PWR_VDDIOCTRL);
338 tmp_r &= ~(HW_POWER_VDDIOCTRL_BO_OFFSET | HW_POWER_VDDIOCTRL_TRG);
339 tmp_r |= __SHIFTIN(((target - brownout) / 25),
341 tmp_r |= __SHIFTIN(((target - 2800) / 25), HW_POWER_VDDIOCTRL_TRG);
342 REG_WR(PWR_VDDIOCTRL, tmp_r);
348 tmp_r = REG_RD(PWR_VDDIOCTRL);
349 tmp_r |= HW_POWER_VDDIOCTRL_PWDN_BRNOUT;
350 REG_WR(PWR_VDDIOCTRL, tmp_r);
362 uint32_t tmp_r;
364 tmp_r = REG_RD(CLKCTRL_SSP);
365 tmp_r &= ~HW_CLKCTRL_SSP_CLKGATE;
366 REG_WR(CLKCTRL_SSP, tmp_r);
371 tmp_r = REG_RD(CLKCTRL_SSP);
372 tmp_r &= ~HW_CLKCTRL_SSP_DIV;
373 tmp_r |= __SHIFTIN(div, HW_CLKCTRL_SSP_DIV);
374 REG_WR(CLKCTRL_SSP, tmp_r);
386 uint32_t tmp_r;
392 tmp_r = (*io_frac)<<24;
393 tmp_r &= ~(HW_CLKCTRL_FRAC_CLKGATEIO | HW_CLKCTRL_FRAC_IOFRAC);
394 tmp_r |= __SHIFTIN(frac, HW_CLKCTRL_FRAC_IOFRAC);
396 *io_frac = (uint8_t)(tmp_r>>24);