Cross Reference: /src/sys/dev/pci/ixgbe/ixgbe_dcb

Lines Matching defs:hw
46  * @hw: pointer to hardware structure
52 s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
66 		stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
68 		stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));
70 			(((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);
72 		stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
74 		stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));
76 			(((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);
79 		stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));
87  * @hw: pointer to hardware structure
93 s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
106 		stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
108 		stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
116  * @hw: pointer to hardware structure
125 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
139 	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
151 	IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
164 		IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
172 	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
179  * @hw: pointer to hardware structure
187 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
195 		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
196 		IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
212 		IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
220 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
227  * @hw: pointer to hardware structure
236 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
250 	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
262 	IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
276 		IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
285 	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
292  * @hw: pointer to hardware structure
298 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
304 	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
307 	reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
317 	if (hw->mac.type >= ixgbe_mac_X540)
323 	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
343 			reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
344 			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
345 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
354 			reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
355 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
358 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
362 		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
363 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
367 	reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
369 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
372 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
379  * @hw: pointer to hardware structure
385 s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,
411 			IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
439 			IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
456 			IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
476 			IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
488 			IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);
498 			IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);
506  * @hw: pointer to hardware structure
511 s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
518 	reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
520 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
522 	reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
557 	IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
568 	IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
572 		IXGBE_WRITE_REG(hw, IXGBE_QDE,
576 	reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
578 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
581 	reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
583 	IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
590  * @hw: pointer to hardware structure
600 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
606 	ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
608 	ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
610 	ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,