Cross Reference: /src/sys/dev/pci/ixgbe/ixgbe

Lines Matching defs:reg_addr
352  * @reg_addr: 32 bit address of PHY register to read
356 static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
363 	command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
399  * @reg_addr: 32 bit PHY register to write
403 static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
413 	command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
629 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
632 	UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
636 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
639 	UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
1304  * @reg_addr: 32 bit PHY register to write
1308 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1323 	command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1350  * @reg_addr: 32 bit PHY register to write
1354 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1369 	command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1465  * @reg_addr: 32 bit PHY register to write
1469 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1482 	write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1495  * @reg_addr: 32 bit PHY register to write
1499 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1515 	hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
4549  * @reg_addr: 32 bit address of PHY register to read
4557 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4568 	status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4578  * @reg_addr: 32 bit PHY register to write
4585 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4594 		status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,