Cross Reference: /xsrc/external/mit/MesaLib/dist/src/amd/compiler/aco

Lines Matching refs:regClass
510                   [](const Definition& def) { return def.regClass().type() == RegType::vgpr; });
519                    [](const Definition& def) { return def.regClass().is_subdword(); });
553       if (temp.regClass() == instr->definitions[0].regClass())
672       if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) {
986          instr->operands[i] = Operand(instr->operands[i].regClass());
988       while (info.is_temp() && info.temp.regClass() == instr->operands[i].getTemp().regClass()) {
1123                     base.regClass() == v1 && mubuf.offset + offset < 4096) {
1131                     base.regClass() == s1 && mubuf.offset + offset < 4096) {
1147              base.regClass() == instr->operands[i].regClass() &&
1192                     base.regClass() == s1 && offset <= 0xFFFFF && ctx.program->chip_class >= GFX9) {
1265                        instr->operands[0].regClass() == instr->definitions[0].regClass();
1295                 ops[i].regClass() == ctx.info[ops[i].tempId()].temp.regClass())
1390           instr->operands[0].regClass() != instr->definitions[0].regClass()) {
1404                 ctx.info[op.tempId()].temp.type() == instr->definitions[0].regClass().type())
1543          all_same_temp = instr->definitions[0].regClass() == instr->operands[0].regClass();
1683          if (instr->operands[0].regClass() == v1 && parse_insert(instr.get()))
1690          if (instr->operands[0].regClass() == v1)
1758    if (instr->definitions[0].regClass() != ctx.program->lane_mask)
1856    if (instr->definitions[0].regClass() != ctx.program->lane_mask)
1958    if (instr->definitions[0].regClass() != ctx.program->lane_mask)
3624    assert(instr->operands[0].regClass() == s1);
3625    assert(instr->operands[1].regClass() == s1);