Cross Reference: /xsrc/external/mit/MesaLib/dist/src/amd/compiler/aco

Lines Matching refs:check
83    auto check = [&program, &is_valid](bool success, const char* msg,
116          /* check base format */
139          check(base_format == instr_info.format[(int)instr->opcode],
142          /* check VOP3 modifiers */
144             check(base_format == Format::VOP2 || base_format == Format::VOP1 ||
149          /* check SDWA */
151             check(base_format == Format::VOP2 || base_format == Format::VOP1 ||
155             check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
158             check(sdwa.omod == 0 || program->chip_class >= GFX9,
161                check(sdwa.clamp == false || program->chip_class == GFX8,
163                check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
168                check(def.bytes() <= 4, "SDWA definitions must not be larger than 4 bytes",
170                check(def.bytes() >= sdwa.dst_sel.size() + sdwa.dst_sel.offset(),
172                check(
175                check(sdwa.dst_sel.offset() % sdwa.dst_sel.size() == 0, "Invalid selection offset",
177                check(def.bytes() == 4 || def.bytes() == sdwa.dst_sel.size(),
180                check(def.bytes() == 4 || sdwa.dst_sel.offset() == 0,
186                check(op.bytes() <= 4, "SDWA operands must not be larger than 4 bytes", instr.get());
187                check(op.bytes() >= sdwa.sel[i].size() + sdwa.sel[i].offset(),
189                check(sdwa.sel[i].size() == 1 || sdwa.sel[i].size() == 2 || sdwa.sel[i].size() == 4,
191                check(sdwa.sel[i].offset() % sdwa.sel[i].size() == 0, "Invalid selection offset",
195                check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
199                check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
220             check(sdwa_opcodes || feature_mac, "SDWA can't be used with this opcode", instr.get());
223          /* check opsel */
226             check(vop3.opsel == 0 || program->chip_class >= GFX9,
233                   check((vop3.opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get());
236                check((vop3.opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition",
243                   check((vop3p.opsel_lo & (1 << i)) == 0 && (vop3p.opsel_hi & (1 << i)) == 0,
246             check(instr->definitions[0].regClass() == v1, "VOP3P must have v1 definition",
250          /* check for undefs */
258                check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
260                check(instr->operands[i].isFixed() || instr->operands[i].isTemp() ||
266          /* check subdword definitions */
269                check(instr->isPseudo() || instr->definitions[i].bytes() <= 4,
275             /* check literals */
282                check(!instr->isDPP() && !instr->isSDWA() &&
287                check(literal.isUndefined() || (literal.size() == op.size() &&
291                check(instr->isSALU() || instr->isVOP3() || instr->isVOP3P() || i == 0 || i == 2,
295             /* check num sgprs for VALU */
313                   check(instr->definitions[0].getTemp().type() == RegType::sgpr,
316                   check(instr->definitions[0].getTemp().type() == RegType::vgpr,
327                      check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
330                      check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr &&
337                      check(i != 0 || (op.isTemp() && op.regClass().type() == RegType::vgpr),
339                      check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
347                      check(i != 2 || (op.isTemp() && op.regClass().type() == RegType::vgpr &&
350                      check(i == 2 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
356                      check(scalar_mask & (1 << i), "Wrong source position for SGPR argument",
366                      check(scalar_mask & (1 << i), "Wrong source position for constant argument",
369                check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit,
374                check(instr->definitions[0].getTemp().type() == RegType::sgpr,
377                   check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
388                   check(op.bytes() < 4 || size % 4 == 0, "Operand is not aligned", instr.get());
391                check(size == instr->definitions[0].bytes(),
395                      check(op.isConstant() || op.regClass().type() == RegType::sgpr,
400                check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(),
402                check((instr->operands[1].constantValue() + 1) * instr->definitions[0].bytes() <=
405                check(instr->definitions[0].getTemp().type() == RegType::vgpr ||
408                check(program->chip_class >= GFX9 ||
413                check(instr->operands[0].isTemp(), "Operand must be a temporary", instr.get());
418                check(size == instr->operands[0].bytes(),
422                      check(def.regClass().type() == RegType::vgpr,
426                      check(program->chip_class >= GFX9 || !def.regClass().is_subdword(),
430                check(instr->definitions.size() == instr->operands.size(),
433                   check(instr->definitions[i].bytes() == instr->operands[i].bytes(),
436                      check((instr->definitions[i].getTemp().type() ==
441                      check(instr->definitions[i].regClass().is_linear_vgpr() ==
445                      check(!instr->definitions[i].regClass().is_linear_vgpr(),
451                check(instr->operands.size() == block.logical_preds.size(),
453                check(instr->definitions[0].getTemp().type() == RegType::vgpr,
456                   check(instr->definitions[0].size() == op.size(),
460                   check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type",
462                   check(instr->definitions[0].size() == op.size(),
465                check(instr->operands.size() == block.linear_preds.size(),
469                check(instr->operands[0].isTemp(), "Data operand must be temporary", instr.get());
470                check(instr->operands[1].isConstant(), "Index must be constant", instr.get());
472                   check(instr->operands[3].isConstant(), "Sign-extend flag must be constant",
475                check(instr->definitions[0].getTemp().type() != RegType::sgpr ||
480                   check(instr->operands[0].bytes() == instr->definitions[0].bytes(),
484                   check(instr->definitions.size() >= 2 && instr->definitions[1].isFixed() &&
492                   check(op_bits == 8 || op_bits == 16, "Size must be 8 or 16", instr.get());
493                   check(op_bits < data_bits, "Size must be smaller than source", instr.get());
495                   check(op_bits == 8 || op_bits == 16 || op_bits == 32,
497                   check(data_bits >= op_bits, "Can't extract more bits than what the data has.",
502                check(instr->operands[1].constantValue() < comp, "Index must be in-bounds",
509                check(op.regClass().type() == RegType::vgpr,
515                check(instr->definitions[0].regClass().type() == RegType::sgpr ||
519                check(instr->definitions[0].regClass().type() == RegType::vgpr,
527                check((instr->operands[0].isFixed() && !instr->operands[0].isConstant()) ||
532                check(instr->operands[1].isConstant() ||
537                check(instr->definitions[0].getTemp().type() == RegType::sgpr,
543             check(instr->operands.size() > 1, "VMEM instructions must have at least one operand",
545             check(instr->operands[1].hasRegClass() &&
548             check(
551             check(instr->operands.size() < 4 ||
558             check(instr->operands.size() >= 4, "MIMG instructions must have at least 4 operands",
560             check(instr->operands[0].hasRegClass() &&
564                check(instr->operands[1].regClass() == s4,
569                check(instr->definitions.empty() ||
576             check(instr->operands.size() == 4 || program->chip_class >= GFX10,
580                   check(instr->operands[i].hasRegClass() &&
584                   check(instr->operands[i].regClass() == v1, "MIMG VADDR must be v1 if NSA is used",
588             check(instr->definitions.empty() ||
596                check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
600                check(instr->definitions[0].getTemp().type() == RegType::vgpr,
606                check(instr->operands[i].hasRegClass() &&
612             check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR",
617             check(
620             check(instr->operands[1].hasRegClass() &&
624                check(instr->definitions[0].getTemp().type() == RegType::vgpr,
627                check(instr->operands[2].regClass().type() == RegType::vgpr,
954       /* check live out */
971          /* check killed p_phi sgpr operands */