Lines Matching refs:bits

11474     {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
11475     {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
11476     {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
11477     {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
11478     {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
11479     {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
11480     {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
11481     {"bits": [30, 30], "name": "ENABLE"},
11482     {"bits": [31, 31], "name": "DISABLE_ROP3"}
11487     {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
11488     {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
11489     {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
11490     {"bits": [12, 14], "name": "NUM_SAMPLES"},
11491     {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
11492     {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
11493     {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"},
11494     {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"}
11499     {"bits": [0, 13], "name": "MIP0_HEIGHT"},
11500     {"bits": [14, 27], "name": "MIP0_WIDTH"},
11501     {"bits": [28, 31], "name": "MAX_MIP"}
11506     {"bits": [0, 12], "name": "MIP0_DEPTH"},
11507     {"bits": [13, 13], "name": "META_LINEAR"},
11508     {"bits": [14, 18], "name": "COLOR_SW_MODE"},
11509     {"bits": [19, 23], "name": "FMASK_SW_MODE"},
11510     {"bits": [24, 25], "name": "RESOURCE_TYPE"},
11511     {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"},
11512     {"bits": [27, 29], "name": "RESOURCE_LEVEL"},
11513     {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"},
11514     {"bits": [31, 31], "name": "VRS_RATE_HINT_ENABLE"}
11519     {"bits": [0, 7], "name": "BASE_256B"}
11524     {"bits": [0, 13], "name": "TILE_MAX"}
11529     {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11530     {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
11531     {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
11532     {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
11533     {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
11534     {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
11535     {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
11536     {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
11537     {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
11538     {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11539     {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
11540     {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"},
11541     {"bits": [21, 21], "name": "SKIP_LOW_COMP_RATIO"},
11542     {"bits": [22, 22], "name": "DCC_COMPRESS_DISABLE"}
11547     {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
11548     {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
11549     {"bits": [7, 7], "name": "LINEAR_GENERAL"},
11550     {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
11551     {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
11552     {"bits": [13, 13], "name": "FAST_CLEAR"},
11553     {"bits": [14, 14], "name": "COMPRESSION"},
11554     {"bits": [15, 15], "name": "BLEND_CLAMP"},
11555     {"bits": [16, 16], "name": "BLEND_BYPASS"},
11556     {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
11557     {"bits": [18, 18], "name": "ROUND_MODE"},
11558     {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
11559     {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
11560     {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
11561     {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
11562     {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
11563     {"bits": [28, 28], "name": "DCC_ENABLE"},
11564     {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
11565     {"bits": [31, 31], "name": "NBC_TILING"}
11570     {"bits": [0, 10], "name": "TILE_MAX"},
11571     {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
11576     {"bits": [0, 21], "name": "TILE_MAX"}
11581     {"bits": [0, 12], "name": "SLICE_START"},
11582     {"bits": [13, 25], "name": "SLICE_MAX"},
11583     {"bits": [26, 29], "name": "MIP_LEVEL"}
11588     {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
11589     {"bits": [1, 1], "name": "ENABLE_1FRAG_PS_INVOKE"},
11590     {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
11591     {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
11592     {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
11597     {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
11598     {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
11599     {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
11600     {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
11605     {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11606     {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
11607     {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
11608     {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
11609     {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11610     {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
11611     {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
11612     {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
11617     {"bits": [0, 8], "name": "PERF_SEL"},
11618     {"bits": [10, 18], "name": "PERF_SEL1"},
11619     {"bits": [20, 23], "name": "CNTR_MODE"},
11620     {"bits": [24, 27], "name": "PERF_MODE1"},
11621     {"bits": [28, 31], "name": "PERF_MODE"}
11626     {"bits": [0, 8], "name": "PERF_SEL2"},
11627     {"bits": [10, 18], "name": "PERF_SEL3"},
11628     {"bits": [24, 27], "name": "PERF_MODE3"},
11629     {"bits": [28, 31], "name": "PERF_MODE2"}
11634     {"bits": [0, 8], "name": "PERF_SEL"},
11635     {"bits": [28, 31], "name": "PERF_MODE"}
11640     {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
11641     {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
11642     {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
11643     {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
11644     {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
11645     {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
11646     {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
11647     {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
11648     {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
11649     {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
11650     {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
11651     {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
11656     {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
11657     {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
11658     {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
11659     {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
11660     {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
11661     {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
11662     {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
11663     {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
11664     {"bits": [24, 24], "name": "CMASK_L3_BYPASS"},
11665     {"bits": [25, 25], "name": "FMASK_L3_BYPASS"},
11666     {"bits": [26, 26], "name": "DCC_L3_BYPASS"},
11667     {"bits": [27, 27], "name": "COLOR_L3_BYPASS"},
11668     {"bits": [30, 30], "name": "FMASK_BIG_PAGE"},
11669     {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
11674     {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
11675     {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
11676     {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
11677     {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
11678     {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
11679     {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
11680     {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
11681     {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
11686     {"bits": [0, 3], "name": "TARGET0_ENABLE"},
11687     {"bits": [4, 7], "name": "TARGET1_ENABLE"},
11688     {"bits": [8, 11], "name": "TARGET2_ENABLE"},
11689     {"bits": [12, 15], "name": "TARGET3_ENABLE"},
11690     {"bits": [16, 19], "name": "TARGET4_ENABLE"},
11691     {"bits": [20, 23], "name": "TARGET5_ENABLE"},
11692     {"bits": [24, 27], "name": "TARGET6_ENABLE"},
11693     {"bits": [28, 31], "name": "TARGET7_ENABLE"}
11698     {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
11703     {"bits": [0, 10], "name": "INDEX"}
11708     {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
11709     {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
11710     {"bits": [2, 2], "name": "FORCE_START_AT_000"},
11711     {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
11712     {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
11713     {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
11714     {"bits": [6, 6], "name": "ORDER_MODE"},
11715     {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
11716     {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
11717     {"bits": [12, 12], "name": "RESERVED"},
11718     {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
11719     {"bits": [14, 14], "name": "RESTORE"},
11720     {"bits": [15, 15], "name": "CS_W32_EN"}
11725     {"bits": [0, 9], "name": "OFF_DELAY"},
11726     {"bits": [10, 10], "name": "IMMEDIATE"}
11731     {"bits": [0, 1], "name": "SEND_SEID"},
11732     {"bits": [2, 2], "name": "RESERVED2"},
11733     {"bits": [3, 3], "name": "RESERVED3"},
11734     {"bits": [4, 4], "name": "RESERVED4"},
11735     {"bits": [5, 16], "name": "WAVE_ID_BASE"}
11740     {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
11741     {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
11746     {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
11751     {"bits": [0, 7], "name": "DATA"}
11756     {"bits": [0, 5], "name": "VGPRS"},
11757     {"bits": [6, 9], "name": "SGPRS"},
11758     {"bits": [10, 11], "name": "PRIORITY"},
11759     {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11760     {"bits": [20, 20], "name": "PRIV"},
11761     {"bits": [21, 21], "name": "DX10_CLAMP"},
11762     {"bits": [23, 23], "name": "IEEE_MODE"},
11763     {"bits": [24, 24], "name": "BULKY"},
11764     {"bits": [26, 26], "name": "FP16_OVFL"},
11765     {"bits": [29, 29], "name": "WGP_MODE"},
11766     {"bits": [30, 30], "name": "MEM_ORDERED"},
11767     {"bits": [31, 31], "name": "FWD_PROGRESS"}
11772     {"bits": [0, 0], "name": "SCRATCH_EN"},
11773     {"bits": [1, 5], "name": "USER_SGPR"},
11774     {"bits": [6, 6], "name": "TRAP_PRESENT"},
11775     {"bits": [7, 7], "name": "TGID_X_EN"},
11776     {"bits": [8, 8], "name": "TGID_Y_EN"},
11777     {"bits": [9, 9], "name": "TGID_Z_EN"},
11778     {"bits": [10, 10], "name": "TG_SIZE_EN"},
11779     {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
11780     {"bits": [13, 14], "name": "EXCP_EN_MSB"},
11781     {"bits": [15, 23], "name": "LDS_SIZE"},
11782     {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11787     {"bits": [0, 3], "name": "SHARED_VGPR_CNT"}
11792     {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
11797     {"bits": [0, 29], "name": "PAYLOAD"},
11798     {"bits": [30, 30], "name": "IS_EVENT"},
11799     {"bits": [31, 31], "name": "IS_STATE"}
11804     {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
11805     {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
11806     {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
11807     {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
11808     {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
11809     {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
11810     {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
11811     {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
11812     {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
11817     {"bits": [0, 9], "name": "WAVES_PER_SH"},
11818     {"bits": [12, 15], "name": "TG_PER_CU"},
11819     {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
11820     {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
11821     {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
11822     {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
11827     {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
11832     {"bits": [0, 11], "name": "WAVES"},
11833     {"bits": [12, 24], "name": "WAVESIZE"}
11838     {"bits": [0, 3], "name": "DATA"}
11843     {"bits": [0, 15], "name": "ADDR"}
11848     {"bits": [0, 3], "name": "INDEX"},
11849     {"bits": [30, 30], "name": "CLEAR"},
11850     {"bits": [31, 31], "name": "ENABLE"}
11855     {"bits": [0, 2], "name": "INDEX"},
11856     {"bits": [30, 30], "name": "ALWAYS"},
11857     {"bits": [31, 31], "name": "ENABLE"}
11862     {"bits": [0, 4], "name": "INDEX"},
11863     {"bits": [30, 30], "name": "CLEAR"},
11864     {"bits": [31, 31], "name": "ENABLE"}
11869     {"bits": [0, 9], "name": "PERF_SEL2"},
11870     {"bits": [10, 19], "name": "PERF_SEL3"},
11871     {"bits": [24, 27], "name": "CNTR_MODE3"},
11872     {"bits": [28, 31], "name": "CNTR_MODE2"}
11877     {"bits": [0, 9], "name": "PERF_SEL"},
11878     {"bits": [10, 19], "name": "PERF_SEL1"},
11879     {"bits": [20, 23], "name": "SPM_MODE"},
11880     {"bits": [24, 27], "name": "CNTR_MODE1"},
11881     {"bits": [28, 31], "name": "CNTR_MODE0"}
11886     {"bits": [0, 4], "name": "INDEX"},
11887     {"bits": [30, 30], "name": "ALWAYS"},
11888     {"bits": [31, 31], "name": "ENABLE"}
11893     {"bits": [0, 15], "name": "MEM_ADDR_HI"},
11894     {"bits": [16, 16], "name": "CS_PS_SEL"},
11895     {"bits": [25, 26], "name": "CACHE_POLICY"},
11896     {"bits": [29, 31], "name": "COMMAND"}
11901     {"bits": [2, 31], "name": "MEM_ADDR_LO"}
11906     {"bits": [0, 15], "name": "IB1_BASE_HI"}
11911     {"bits": [2, 31], "name": "IB1_BASE_LO"}
11916     {"bits": [0, 19], "name": "IB1_BUFSZ"}
11921     {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
11926     {"bits": [0, 19], "name": "IB1_OFFSET"}
11931     {"bits": [0, 15], "name": "IB2_BASE_HI"}
11936     {"bits": [2, 31], "name": "IB2_BASE_LO"}
11941     {"bits": [0, 19], "name": "IB2_BUFSZ"}
11946     {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
11951     {"bits": [0, 15], "name": "INIT_BASE_HI"}
11956     {"bits": [5, 31], "name": "INIT_BASE_LO"}
11961     {"bits": [0, 11], "name": "INIT_BUFSZ"}
11966     {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
11971     {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
11976     {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
11977     {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
11978     {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
11979     {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
11980     {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
11981     {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
11982     {"bits": [23, 23], "name": "TC_ACTION_ENA"},
11983     {"bits": [25, 25], "name": "CB_ACTION_ENA"},
11984     {"bits": [26, 26], "name": "DB_ACTION_ENA"},
11985     {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
11986     {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
11987     {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
11988     {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
11993     {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
11998     {"bits": [0, 5], "name": "START_DELAY_COUNT"}
12003     {"bits": [24, 25], "name": "MEID"},
12004     {"bits": [31, 31], "name": "STATUS"}
12009     {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
12010     {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
12011     {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
12012     {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
12013     {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
12014     {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
12015     {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
12016     {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
12017     {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
12018     {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
12019     {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
12020     {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
12021     {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
12022     {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
12023     {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
12024     {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
12025     {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
12026     {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
12027     {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
12028     {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
12029     {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
12030     {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
12031     {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
12032     {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
12033     {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
12034     {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
12035     {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
12036     {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
12041     {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
12042     {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
12043     {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
12044     {"bits": [7, 7], "name": "MES_TC_BUSY"},
12045     {"bits": [8, 8], "name": "MES_DMA_BUSY"},
12046     {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
12047     {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
12048     {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
12049     {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
12054     {"bits": [0, 5], "name": "FREE_COUNT"}
12059     {"bits": [0, 3], "name": "COUNT"}
12064     {"bits": [0, 15], "name": "PRIV_VIOLATION_ADDR"}
12069     {"bits": [0, 8], "name": "SCRATCH_INDEX"},
12070     {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
12075     {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
12076     {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
12077     {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
12078     {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
12079     {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
12080     {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
12081     {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
12082     {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
12083     {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
12084     {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
12085     {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
12086     {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
12087     {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
12088     {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
12089     {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
12094     {"bits": [0, 0], "name": "MEC1_BUSY"},
12095     {"bits": [1, 1], "name": "MEC2_BUSY"},
12096     {"bits": [2, 2], "name": "DC0_BUSY"},
12097     {"bits": [3, 3], "name": "DC1_BUSY"},
12098     {"bits": [4, 4], "name": "RCIU1_BUSY"},
12099     {"bits": [5, 5], "name": "RCIU2_BUSY"},
12100     {"bits": [6, 6], "name": "ROQ1_BUSY"},
12101     {"bits": [7, 7], "name": "ROQ2_BUSY"},
12102     {"bits": [10, 10], "name": "TCIU_BUSY"},
12103     {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
12104     {"bits": [12, 12], "name": "QU_BUSY"},
12105     {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
12106     {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
12107     {"bits": [15, 15], "name": "GCRIU_BUSY"},
12108     {"bits": [16, 16], "name": "MES_BUSY"},
12109     {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
12110     {"bits": [18, 18], "name": "RCIU3_BUSY"},
12111     {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
12112     {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
12113     {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
12114     {"bits": [31, 31], "name": "CPC_BUSY"}
12119     {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
12120     {"bits": [1, 1], "name": "CSF_RING_BUSY"},
12121     {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
12122     {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
12123     {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
12124     {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
12125     {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
12126     {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
12127     {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
12128     {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
12129     {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
12130     {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
12131     {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
12132     {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
12133     {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
12134     {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
12135     {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
12136     {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
12137     {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
12138     {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
12139     {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
12140     {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
12141     {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
12142     {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
12143     {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
12144     {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
12145     {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
12146     {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
12147     {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
12148     {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
12149     {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
12150     {"bits": [31, 31], "name": "HQD_IB_BUSY"}
12155     {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
12156     {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
12157     {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
12158     {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
12159     {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
12160     {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
12161     {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
12162     {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
12163     {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
12168     {"bits": [0, 2], "name": "FREE_COUNT"}
12173     {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
12174     {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
12175     {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
12176     {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
12177     {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
12178     {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
12179     {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
12180     {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
12181     {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
12182     {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
12183     {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
12184     {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
12185     {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
12190     {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
12191     {"bits": [1, 1], "name": "CSF_BUSY"},
12192     {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
12193     {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
12194     {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
12195     {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
12196     {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
12197     {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
12198     {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
12199     {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
12200     {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
12201     {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
12202     {"bits": [14, 14], "name": "TCIU_BUSY"},
12203     {"bits": [15, 15], "name": "HQD_BUSY"},
12204     {"bits": [16, 16], "name": "PRT_BUSY"},
12205     {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
12206     {"bits": [18, 18], "name": "RCIU_BUSY"},
12207     {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
12208     {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
12209     {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
12210     {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
12211     {"bits": [23, 23], "name": "GCRIU_BUSY"},
12212     {"bits": [24, 24], "name": "MES_HQD_BUSY"},
12213     {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
12214     {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
12215     {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
12216     {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
12217     {"bits": [31, 31], "name": "CPF_BUSY"}
12222     {"bits": [0, 15], "name": "DB_BASE_HI"}
12227     {"bits": [2, 31], "name": "DB_BASE_LO"}
12232     {"bits": [0, 19], "name": "DB_BUFSZ"}
12237     {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
12242     {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
12243     {"bits": [1, 1], "name": "WATCH_CONTROL"},
12244     {"bits": [4, 5], "name": "MIN_AVAILSZ"},
12245     {"bits": [16, 24], "name": "BUFFER_DEPTH"},
12246     {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
12247     {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
12248     {"bits": [30, 31], "name": "PIO_COUNT"}
12253     {"bits": [0, 15], "name": "ADDR_HI"},
12254     {"bits": [16, 31], "name": "RSVD"}
12259     {"bits": [0, 1], "name": "RSVD"},
12260     {"bits": [2, 31], "name": "ADDR_LO"}
12265     {"bits": [0, 25], "name": "BYTE_COUNT"},
12266     {"bits": [26, 26], "name": "SAS"},
12267     {"bits": [27, 27], "name": "DAS"},
12268     {"bits": [28, 28], "name": "SAIC"},
12269     {"bits": [29, 29], "name": "DAIC"},
12270     {"bits": [30, 30], "name": "RAW_WAIT"},
12271     {"bits": [31, 31], "name": "DIS_WC"}
12276     {"bits": [0, 15], "name": "DST_ADDR_HI"}
12281     {"bits": [0, 15], "name": "SRC_ADDR_HI"}
12286     {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
12287     {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
12288     {"bits": [15, 15], "name": "SRC_VOLATLE"},
12289     {"bits": [20, 21], "name": "DST_SELECT"},
12290     {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
12291     {"bits": [27, 27], "name": "DST_VOLATLE"},
12292     {"bits": [29, 30], "name": "SRC_SELECT"}
12297     {"bits": [0, 25], "name": "DMA_READ_TAG"},
12298     {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
12303     {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
12304     {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
12305     {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
12306     {"bits": [8, 8], "name": "MODE"}
12311     {"bits": [0, 15], "name": "MIN"},
12312     {"bits": [16, 31], "name": "MAX"}
12317     {"bits": [0, 15], "name": "ADDR_HI"}
12322     {"bits": [2, 31], "name": "ADDR_LO"}
12327     {"bits": [16, 17], "name": "DST_SEL"},
12328     {"bits": [20, 21], "name": "ACTION_PIPE_ID"},
12329     {"bits": [22, 23], "name": "ACTION_ID"},
12330     {"bits": [24, 26], "name": "INT_SEL"},
12331     {"bits": [29, 31], "name": "DATA_SEL"}
12336     {"bits": [12, 23], "name": "GCR_CNTL"},
12337     {"bits": [25, 26], "name": "CACHE_POLICY"},
12338     {"bits": [27, 27], "name": "EOP_VOLATILE"},
12339     {"bits": [28, 28], "name": "EXECUTE"}
12344     {"bits": [0, 19], "name": "IB2_OFFSET"}
12349     {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
12354     {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
12359     {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
12364     {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
12365     {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
12366     {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
12367     {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
12368     {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
12369     {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
12370     {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
12371     {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
12372     {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
12373     {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
12374     {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
12375     {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
12376     {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
12381     {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
12382     {"bits": [31, 31], "name": "STATUS"}
12387     {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
12388     {"bits": [22, 23], "name": "CACHE_POLICY"}
12393     {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
12398     {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
12399     {"bits": [22, 23], "name": "CACHE_POLICY"}
12404     {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
12409     {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
12410     {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
12411     {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
12412     {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
12417     {"bits": [31, 31], "name": "PERFMON_ENABLE"}
12422     {"bits": [0, 1], "name": "STATUS"}
12427     {"bits": [0, 7], "name": "IB_EN"}
12432     {"bits": [0, 0], "name": "CONFIG_REG_EN"},
12433     {"bits": [1, 1], "name": "CNTX_REG_EN"},
12434     {"bits": [15, 15], "name": "UCONFIG_REG_EN"},
12435     {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
12436     {"bits": [24, 24], "name": "SH_CS_REG_EN"}
12441     {"bits": [0, 1], "name": "PIPE_ID"}
12446     {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
12451     {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
12456     {"bits": [25, 26], "name": "CACHE_POLICY"}
12461     {"bits": [0, 0], "name": "NOT_VISIBLE"}
12466     {"bits": [0, 19], "name": "RB_OFFSET"}
12471     {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
12472     {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
12473     {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
12474     {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
12475     {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
12476     {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
12477     {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
12478     {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
12483     {"bits": [0, 15], "name": "SEM_ADDR_HI"},
12484     {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
12485     {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
12486     {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
12487     {"bits": [29, 31], "name": "SEM_SELECT"}
12492     {"bits": [0, 0], "name": "SEM_PRIV"},
12493     {"bits": [3, 31], "name": "SEM_ADDR_LO"}
12498     {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
12503     {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
12508     {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
12513     {"bits": [0, 15], "name": "ST_BASE_HI"}
12518     {"bits": [2, 31], "name": "ST_BASE_LO"}
12523     {"bits": [0, 19], "name": "ST_BUFSZ"}
12528     {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
12533     {"bits": [0, 3], "name": "VMID"}
12538     {"bits": [0, 2], "name": "SRC_STATE_ID"}
12543     {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
12544     {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
12545     {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
12546     {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
12547     {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
12548     {"bits": [16, 16], "name": "OFFSET_ROUND"}
12553     {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
12554     {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
12555     {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
12556     {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
12557     {"bits": [4, 6], "name": "SAMPLE_RATE"},
12558     {"bits": [8, 11], "name": "ZPASS_ENABLE"},
12559     {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
12560     {"bits": [16, 19], "name": "SFAIL_ENABLE"},
12561     {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
12562     {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
12563     {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
12568     {"bits": [0, 0], "name": "STENCIL_ENABLE"},
12569     {"bits": [1, 1], "name": "Z_ENABLE"},
12570     {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
12571     {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
12572     {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
12573     {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
12574     {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
12575     {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
12576     {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
12577     {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
12582     {"bits": [0, 13], "name": "X_MAX"},
12583     {"bits": [16, 29], "name": "Y_MAX"}
12588     {"bits": [0, 10], "name": "SLICE_START"},
12589     {"bits": [11, 12], "name": "SLICE_START_HI"},
12590     {"bits": [13, 23], "name": "SLICE_MAX"},
12591     {"bits": [24, 24], "name": "Z_READ_ONLY"},
12592     {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
12593     {"bits": [26, 29], "name": "MIPID"},
12594     {"bits": [30, 31], "name": "SLICE_MAX_HI"}
12599     {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
12600     {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
12601     {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
12606     {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
12607     {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
12608     {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
12609     {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
12610     {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
12611     {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
12612     {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
12613     {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
12614     {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
12615     {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
12616     {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
12617     {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
12622     {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
12623     {"bits": [1, 1], "name": "FULL_CACHE"},
12624     {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
12625     {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
12626     {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
12627     {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
12628     {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
12629     {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
12630     {"bits": [18, 18], "name": "PIPE_ALIGNED"},
12631     {"bits": [19, 20], "enum_ref": "VRSHtileEncoding", "name": "VRS_HTILE_ENCODING"}
12636     {"bits": [0, 30], "name": "COUNT_HI"}
12641     {"bits": [0, 7], "name": "START_X"},
12642     {"bits": [8, 15], "name": "START_Y"},
12643     {"bits": [16, 23], "name": "MAX_X"},
12644     {"bits": [24, 31], "name": "MAX_Y"}
12649     {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
12650     {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
12651     {"bits": [2, 2], "name": "DEPTH_COPY"},
12652     {"bits": [3, 3], "name": "STENCIL_COPY"},
12653     {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
12654     {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
12655     {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
12656     {"bits": [7, 7], "name": "COPY_CENTROID"},
12657     {"bits": [8, 11], "name": "COPY_SAMPLE"},
12658     {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"},
12659     {"bits": [13, 13], "name": "PS_INVOKE_DISABLE"}
12664     {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
12665     {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
12666     {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
12667     {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
12668     {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
12669     {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
12670     {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
12671     {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
12672     {"bits": [11, 11], "name": "FORCE_Z_READ"},
12673     {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
12674     {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
12675     {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
12676     {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
12677     {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
12678     {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
12679     {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
12680     {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
12681     {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
12682     {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
12683     {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
12684     {"bits": [29, 29], "name": "FORCE_Z_VALID"},
12685     {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
12686     {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
12691     {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
12692     {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
12693     {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
12694     {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
12695     {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
12696     {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
12697     {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
12698     {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
12699     {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
12700     {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
12701     {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
12702     {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
12703     {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
12704     {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
12705     {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
12706     {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"},
12707     {"bits": [26, 26], "name": "FORCE_VRS_RATE_FINE"},
12708     {"bits": [27, 28], "name": "CENTROID_COMPUTATION_MODE"}
12713     {"bits": [0, 10], "name": "FIELD_1"},
12714     {"bits": [11, 21], "name": "FIELD_2"}
12719     {"bits": [0, 3], "name": "FIELD_1"},
12720     {"bits": [4, 7], "name": "FIELD_2"},
12721     {"bits": [8, 12], "name": "FIELD_3"},
12722     {"bits": [13, 14], "name": "FIELD_4"},
12723     {"bits": [15, 16], "name": "FIELD_5"},
12724     {"bits": [17, 18], "name": "FIELD_6"},
12725     {"bits": [19, 20], "name": "FIELD_7"},
12726     {"bits": [28, 31], "name": "RESOURCE_LEVEL"}
12731     {"bits": [0, 21], "name": "FIELD_1"}
12736     {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
12737     {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
12738     {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
12739     {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
12740     {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
12741     {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
12742     {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
12743     {"bits": [24, 24], "name": "Z_BIG_PAGE"},
12744     {"bits": [25, 25], "name": "S_BIG_PAGE"},
12745     {"bits": [26, 26], "name": "Z_NOALLOC"},
12746     {"bits": [27, 27], "name": "S_NOALLOC"},
12747     {"bits": [28, 28], "name": "HTILE_NOALLOC"},
12748     {"bits": [29, 29], "name": "ZPCPSD_NOALLOC"}
12753     {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
12754     {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
12755     {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
12756     {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
12757     {"bits": [6, 6], "name": "KILL_ENABLE"},
12758     {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
12759     {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
12760     {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
12761     {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
12762     {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
12763     {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
12764     {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
12765     {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
12766     {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
12767     {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
12768     {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"},
12769     {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"}
12774     {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
12775     {"bits": [4, 11], "name": "COMPAREVALUE0"},
12776     {"bits": [12, 19], "name": "COMPAREMASK0"},
12777     {"bits": [24, 24], "name": "ENABLE0"}
12782     {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
12783     {"bits": [4, 11], "name": "COMPAREVALUE1"},
12784     {"bits": [12, 19], "name": "COMPAREMASK1"},
12785     {"bits": [24, 24], "name": "ENABLE1"}
12790     {"bits": [0, 7], "name": "STENCILTESTVAL"},
12791     {"bits": [8, 15], "name": "STENCILMASK"},
12792     {"bits": [16, 23], "name": "STENCILWRITEMASK"},
12793     {"bits": [24, 31], "name": "STENCILOPVAL"}
12798     {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
12799     {"bits": [8, 15], "name": "STENCILMASK_BF"},
12800     {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
12801     {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
12806     {"bits": [0, 7], "name": "CLEAR"}
12811     {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
12812     {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
12813     {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
12814     {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
12815     {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
12816     {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
12821     {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
12822     {"bits": [4, 8], "name": "SW_MODE"},
12823     {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12824     {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12825     {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12826     {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12827     {"bits": [20, 20], "name": "ITERATE_256"},
12828     {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12829     {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
12834     {"bits": [0, 2], "enum_ref": "VRSCombinerMode", "name": "VRS_OVERRIDE_RATE_COMBINER_MODE"},
12835     {"bits": [4, 5], "name": "VRS_OVERRIDE_RATE_X"},
12836     {"bits": [6, 7], "name": "VRS_OVERRIDE_RATE_Y"}
12841     {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
12842     {"bits": [2, 3], "name": "NUM_SAMPLES"},
12843     {"bits": [4, 8], "name": "SW_MODE"},
12844     {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12845     {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12846     {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12847     {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12848     {"bits": [16, 19], "name": "MAXMIP"},
12849     {"bits": [20, 20], "name": "ITERATE_256"},
12850     {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
12851     {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12852     {"bits": [28, 28], "name": "READ_SIZE"},
12853     {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
12854     {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
12859     {"bits": [0, 7], "name": "BASE_HI"}
12864     {"bits": [0, 2], "name": "NUM_PIPES"},
12865     {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
12866     {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
12867     {"bits": [8, 10], "name": "NUM_PKRS"},
12868     {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
12869     {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
12874     {"bits": [0, 7], "name": "PERF_SEL"},
12875     {"bits": [8, 15], "name": "PERF_SEL_END"},
12876     {"bits": [24, 27], "name": "PERF_MODE"},
12877     {"bits": [28, 28], "name": "ENABLE"},
12878     {"bits": [29, 29], "name": "CLEAR"}
12883     {"bits": [0, 1], "name": "COMPARE_MODE0"},
12884     {"bits": [2, 3], "name": "COMPARE_MODE1"},
12885     {"bits": [4, 5], "name": "COMPARE_MODE2"},
12886     {"bits": [6, 7], "name": "COMPARE_MODE3"},
12887     {"bits": [8, 11], "name": "COMPARE_VALUE0"},
12888     {"bits": [12, 15], "name": "COMPARE_VALUE1"},
12889     {"bits": [16, 19], "name": "COMPARE_VALUE2"},
12890     {"bits": [20, 23], "name": "COMPARE_VALUE3"}
12895     {"bits": [0, 15], "name": "COUNTER_HI"},
12896     {"bits": [16, 31], "name": "COMPARE_VALUE"}
12901     {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
12902     {"bits": [8, 15], "name": "START_TRIGGER"},
12903     {"bits": [16, 23], "name": "STOP_TRIGGER"},
12904     {"bits": [24, 24], "name": "ENABLE_ANY"},
12905     {"bits": [25, 25], "name": "CLEAR_ALL"},
12906     {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
12911     {"bits": [0, 8], "name": "PERF_SEL"},
12912     {"bits": [24, 27], "name": "PERF_MODE"},
12913     {"bits": [28, 31], "name": "CNTL_MODE"}
12918     {"bits": [0, 15], "name": "BASE"},
12919     {"bits": [16, 31], "name": "UNUSED"}
12924     {"bits": [0, 5], "name": "AINC"},
12925     {"bits": [6, 7], "name": "UNUSED1"},
12926     {"bits": [8, 9], "name": "DMODE"},
12927     {"bits": [10, 31], "name": "UNUSED2"}
12932     {"bits": [0, 0], "name": "COMPLETE"},
12933     {"bits": [1, 31], "name": "UNUSED"}
12938     {"bits": [0, 7], "name": "OFFSET0"},
12939     {"bits": [8, 31], "name": "UNUSED"}
12944     {"bits": [0, 7], "name": "OFFSET1"},
12945     {"bits": [8, 31], "name": "UNUSED"}
12950     {"bits": [0, 7], "name": "OP"},
12951     {"bits": [8, 31], "name": "UNUSED"}
12956     {"bits": [0, 15], "name": "SIZE"},
12957     {"bits": [16, 31], "name": "UNUSED"}
12962     {"bits": [0, 0], "name": "FLAG"},
12963     {"bits": [1, 12], "name": "COUNTER"},
12964     {"bits": [13, 13], "name": "TYPE"},
12965     {"bits": [14, 14], "name": "DED"},
12966     {"bits": [15, 15], "name": "RELEASE_ALL"},
12967     {"bits": [16, 26], "name": "HEAD_QUEUE"},
12968     {"bits": [27, 27], "name": "HEAD_VALID"},
12969     {"bits": [28, 28], "name": "HEAD_FLAG"},
12970     {"bits": [29, 29], "name": "HALTED"},
12971     {"bits": [30, 30], "name": "HEAD_QUEUE1"},
12972     {"bits": [31, 31], "name": "UNUSED1"}
12977     {"bits": [0, 15], "name": "RESOURCE_CNT"},
12978     {"bits": [16, 31], "name": "UNUSED"}
12983     {"bits": [0, 5], "name": "INDEX"},
12984     {"bits": [6, 31], "name": "UNUSED"}
12989     {"bits": [0, 15], "name": "DS_ADDRESS"},
12990     {"bits": [16, 19], "name": "CRAWLER_TYPE"},
12991     {"bits": [20, 23], "name": "CRAWLER"},
12992     {"bits": [24, 29], "name": "UNUSED"},
12993     {"bits": [30, 30], "name": "NO_ALLOC"},
12994     {"bits": [31, 31], "name": "ENABLE"}
12999     {"bits": [0, 3], "name": "INDEX"},
13000     {"bits": [4, 31], "name": "UNUSED"}
13005     {"bits": [0, 30], "name": "VALUE"},
13006     {"bits": [31, 31], "name": "INCDEC"}
13011     {"bits": [0, 9], "name": "PERF_SEL0"},
13012     {"bits": [10, 19], "name": "PERF_SEL1"},
13013     {"bits": [20, 23], "name": "CNTR_MODE"},
13014     {"bits": [24, 27], "name": "PERF_MODE0"},
13015     {"bits": [28, 31], "name": "PERF_MODE1"}
13020     {"bits": [0, 9], "name": "PERF_SEL2"},
13021     {"bits": [10, 19], "name": "PERF_SEL3"},
13022     {"bits": [24, 27], "name": "PERF_MODE2"},
13023     {"bits": [28, 31], "name": "PERF_MODE3"}
13028     {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
13029     {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
13030     {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
13031     {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
13036     {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
13041     {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
13042     {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
13047     {"bits": [0, 0], "name": "OVERSUB_EN"},
13048     {"bits": [1, 10], "name": "NUM_PC_LINES"}
13053     {"bits": [0, 2], "name": "RT_SLICE"},
13054     {"bits": [3, 6], "name": "VIEWPORT"},
13055     {"bits": [8, 8], "name": "EN_STEREO"}
13060     {"bits": [0, 0], "name": "EN_USER_VGPR1"},
13061     {"bits": [1, 1], "name": "EN_USER_VGPR2"},
13062     {"bits": [2, 2], "name": "EN_USER_VGPR3"}
13067     {"bits": [0, 7], "name": "INSTANCE_INDEX"},
13068     {"bits": [8, 15], "name": "SA_INDEX"},
13069     {"bits": [16, 23], "name": "SE_INDEX"},
13070     {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
13071     {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
13072     {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
13077     {"bits": [0, 5], "name": "PERF_SEL"},
13078     {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13079     {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13080     {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
13081     {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
13082     {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13083     {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
13084     {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
13085     {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
13086     {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
13087     {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
13088     {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
13089     {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
13090     {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13091     {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
13092     {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13093     {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
13094     {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
13095     {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
13096     {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
13101     {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13102     {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
13103     {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
13104     {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
13105     {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
13106     {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
13107     {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
13108     {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13113     {"bits": [0, 5], "name": "PERF_SEL"},
13114     {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13115     {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13116     {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
13117     {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
13118     {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13119     {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
13120     {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
13121     {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
13122     {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
13123     {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13124     {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
13125     {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13126     {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13127     {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13132     {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
13133     {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
13134     {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
13135     {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
13136     {"bits": [12, 12], "name": "DB_CLEAN"},
13137     {"bits": [13, 13], "name": "CB_CLEAN"},
13138     {"bits": [14, 14], "name": "TA_BUSY"},
13139     {"bits": [15, 15], "name": "GDS_BUSY"},
13140     {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
13141     {"bits": [20, 20], "name": "SX_BUSY"},
13142     {"bits": [21, 21], "name": "GE_BUSY"},
13143     {"bits": [22, 22], "name": "SPI_BUSY"},
13144     {"bits": [23, 23], "name": "BCI_BUSY"},
13145     {"bits": [24, 24], "name": "SC_BUSY"},
13146     {"bits": [25, 25], "name": "PA_BUSY"},
13147     {"bits": [26, 26], "name": "DB_BUSY"},
13148     {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
13149     {"bits": [29, 29], "name": "CP_BUSY"},
13150     {"bits": [30, 30], "name": "CB_BUSY"},
13151     {"bits": [31, 31], "name": "GUI_ACTIVE"}
13156     {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
13157     {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
13158     {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
13159     {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
13160     {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
13161     {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
13162     {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
13163     {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
13164     {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
13165     {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
13166     {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
13167     {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
13168     {"bits": [15, 15], "name": "UTCL2_BUSY"},
13169     {"bits": [16, 16], "name": "EA_BUSY"},
13170     {"bits": [17, 17], "name": "RMI_BUSY"},
13171     {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
13172     {"bits": [19, 19], "name": "SDMA_SCH_RQ_PENDING"},
13173     {"bits": [20, 20], "name": "EA_LINK_BUSY"},
13174     {"bits": [21, 21], "name": "SDMA_BUSY"},
13175     {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
13176     {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
13177     {"bits": [24, 24], "name": "SDMA2_RQ_PENDING"},
13178     {"bits": [25, 25], "name": "SDMA3_RQ_PENDING"},
13179     {"bits": [26, 26], "name": "RLC_BUSY"},
13180     {"bits": [27, 27], "name": "TCP_BUSY"},
13181     {"bits": [28, 28], "name": "CPF_BUSY"},
13182     {"bits": [29, 29], "name": "CPC_BUSY"},
13183     {"bits": [30, 30], "name": "CPG_BUSY"},
13184     {"bits": [31, 31], "name": "CPAXI_BUSY"}
13189     {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
13190     {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"},
13191     {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
13192     {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
13193     {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
13194     {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"},
13195     {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"},
13196     {"bits": [13, 13], "name": "PH_BUSY"},
13197     {"bits": [14, 14], "name": "CH_BUSY"},
13198     {"bits": [15, 15], "name": "GL2CC_BUSY"},
13199     {"bits": [16, 16], "name": "GL1CC_BUSY"},
13200     {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
13201     {"bits": [29, 29], "name": "GUS_BUSY"},
13202     {"bits": [30, 30], "name": "UTCL1_BUSY"},
13203     {"bits": [31, 31], "name": "PMM_BUSY"}
13208     {"bits": [1, 1], "name": "DB_CLEAN"},
13209     {"bits": [2, 2], "name": "CB_CLEAN"},
13210     {"bits": [3, 3], "name": "UTCL1_BUSY"},
13211     {"bits": [4, 4], "name": "TCP_BUSY"},
13212     {"bits": [5, 5], "name": "GL1CC_BUSY"},
13213     {"bits": [21, 21], "name": "RMI_BUSY"},
13214     {"bits": [22, 22], "name": "BCI_BUSY"},
13215     {"bits": [24, 24], "name": "PA_BUSY"},
13216     {"bits": [25, 25], "name": "TA_BUSY"},
13217     {"bits": [26, 26], "name": "SX_BUSY"},
13218     {"bits": [27, 27], "name": "SPI_BUSY"},
13219     {"bits": [29, 29], "name": "SC_BUSY"},
13220     {"bits": [30, 30], "name": "DB_BUSY"},
13221     {"bits": [31, 31], "name": "CB_BUSY"}
13226     {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13227     {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13228     {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13229     {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13230     {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13231     {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
13236     {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13237     {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13238     {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13239     {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13240     {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13241     {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
13242     {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
13243     {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
13244     {"bits": [23, 23], "name": "HW_USE_ONLY"}
13249     {"bits": [0, 0], "name": "UCP_ENA_0"},
13250     {"bits": [1, 1], "name": "UCP_ENA_1"},
13251     {"bits": [2, 2], "name": "UCP_ENA_2"},
13252     {"bits": [3, 3], "name": "UCP_ENA_3"},
13253     {"bits": [4, 4], "name": "UCP_ENA_4"},
13254     {"bits": [5, 5], "name": "UCP_ENA_5"},
13255     {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
13256     {"bits": [14, 15], "name": "PS_UCP_MODE"},
13257     {"bits": [16, 16], "name": "CLIP_DISABLE"},
13258     {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
13259     {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
13260     {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
13261     {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
13262     {"bits": [21, 21], "name": "VTX_KILL_OR"},
13263     {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
13264     {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
13265     {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
13266     {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
13267     {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
13268     {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
13273     {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
13274     {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
13275     {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
13276     {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
13277     {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
13278     {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
13279     {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
13280     {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
13281     {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
13282     {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
13283     {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
13284     {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
13285     {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
13286     {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
13287     {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
13288     {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
13293     {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
13294     {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"},
13295     {"bits": [2, 9], "name": "VERTEX_REUSE_DEPTH"}
13300     {"bits": [0, 2], "enum_ref": "VRSCombinerMode", "name": "VERTEX_RATE_COMBINER_MODE"},
13301     {"bits": [3, 5], "enum_ref": "VRSCombinerMode", "name": "PRIMITIVE_RATE_COMBINER_MODE"},
13302     {"bits": [6, 8], "enum_ref": "VRSCombinerMode", "name": "HTILE_RATE_COMBINER_MODE"},
13303     {"bits": [9, 11], "enum_ref": "VRSCombinerMode", "name": "SAMPLE_ITER_COMBINER_MODE"},
13304     {"bits": [13, 13], "name": "EXPOSE_VRS_PIXELS_MASK"},
13305     {"bits": [14, 14], "name": "CMASK_RATE_HINT_FORCE_ZERO"}
13310     {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
13311     {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
13312     {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
13313     {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
13314     {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
13315     {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
13316     {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
13317     {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
13318     {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
13319     {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
13320     {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
13321     {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
13322     {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
13323     {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
13324     {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
13325     {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
13326     {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
13327     {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
13328     {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
13329     {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
13330     {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
13331     {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
13332     {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
13333     {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
13334     {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
13335     {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
13336     {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"},
13337     {"bits": [28, 28], "name": "USE_VTX_VRS_RATE"},
13338     {"bits": [29, 29], "name": "BYPASS_VTX_RATE_COMBINER"},
13339     {"bits": [30, 30], "name": "BYPASS_PRIM_RATE_COMBINER"}
13344     {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
13345     {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
13346     {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
13347     {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
13348     {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
13349     {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
13350     {"bits": [8, 8], "name": "VTX_XY_FMT"},
13351     {"bits": [9, 9], "name": "VTX_Z_FMT"},
13352     {"bits": [10, 10], "name": "VTX_W0_FMT"},
13353     {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
13358     {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
13359     {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
13360     {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
13361     {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
13362     {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
13363     {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"},
13364     {"bits": [28, 28], "name": "SAMPLE_COVERAGE_ENCODING"},
13365     {"bits": [29, 29], "name": "COVERED_CENTROID_IS_CENTER"}
13370     {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
13371     {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
13376     {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
13377     {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
13382     {"bits": [0, 3], "name": "S0_X"},
13383     {"bits": [4, 7], "name": "S0_Y"},
13384     {"bits": [8, 11], "name": "S1_X"},
13385     {"bits": [12, 15], "name": "S1_Y"},
13386     {"bits": [16, 19], "name": "S2_X"},
13387     {"bits": [20, 23], "name": "S2_Y"},
13388     {"bits": [24, 27], "name": "S3_X"},
13389     {"bits": [28, 31], "name": "S3_Y"}
13394     {"bits": [0, 3], "name": "S4_X"},
13395     {"bits": [4, 7], "name": "S4_Y"},
13396     {"bits": [8, 11], "name": "S5_X"},
13397     {"bits": [12, 15], "name": "S5_Y"},
13398     {"bits": [16, 19], "name": "S6_X"},
13399     {"bits": [20, 23], "name": "S6_Y"},
13400     {"bits": [24, 27], "name": "S7_X"},
13401     {"bits": [28, 31], "name": "S7_Y"}
13406     {"bits": [0, 3], "name": "S8_X"},
13407     {"bits": [4, 7], "name": "S8_Y"},
13408     {"bits": [8, 11], "name": "S9_X"},
13409     {"bits": [12, 15], "name": "S9_Y"},
13410     {"bits": [16, 19], "name": "S10_X"},
13411     {"bits": [20, 23], "name": "S10_Y"},
13412     {"bits": [24, 27], "name": "S11_X"},
13413     {"bits": [28, 31], "name": "S11_Y"}
13418     {"bits": [0, 3], "name": "S12_X"},
13419     {"bits": [4, 7], "name": "S12_Y"},
13420     {"bits": [8, 11], "name": "S13_X"},
13421     {"bits": [12, 15], "name": "S13_Y"},
13422     {"bits": [16, 19], "name": "S14_X"},
13423     {"bits": [20, 23], "name": "S14_Y"},
13424     {"bits": [24, 27], "name": "S15_X"},
13425     {"bits": [28, 31], "name": "S15_Y"}
13430     {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
13431     {"bits": [2, 2], "name": "BIN_SIZE_X"},
13432     {"bits": [3, 3], "name": "BIN_SIZE_Y"},
13433     {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
13434     {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
13435     {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
13436     {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
13437     {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
13438     {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
13439     {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
13440     {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
13441     {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
13446     {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
13447     {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
13452     {"bits": [0, 3], "name": "DISTANCE_0"},
13453     {"bits": [4, 7], "name": "DISTANCE_1"},
13454     {"bits": [8, 11], "name": "DISTANCE_2"},
13455     {"bits": [12, 15], "name": "DISTANCE_3"},
13456     {"bits": [16, 19], "name": "DISTANCE_4"},
13457     {"bits": [20, 23], "name": "DISTANCE_5"},
13458     {"bits": [24, 27], "name": "DISTANCE_6"},
13459     {"bits": [28, 31], "name": "DISTANCE_7"}
13464     {"bits": [0, 3], "name": "DISTANCE_8"},
13465     {"bits": [4, 7], "name": "DISTANCE_9"},
13466     {"bits": [8, 11], "name": "DISTANCE_10"},
13467     {"bits": [12, 15], "name": "DISTANCE_11"},
13468     {"bits": [16, 19], "name": "DISTANCE_12"},
13469     {"bits": [20, 23], "name": "DISTANCE_13"},
13470     {"bits": [24, 27], "name": "DISTANCE_14"},
13471     {"bits": [28, 31], "name": "DISTANCE_15"}
13476     {"bits": [0, 14], "name": "TL_X"},
13477     {"bits": [16, 30], "name": "TL_Y"}
13482     {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
13487     {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
13488     {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
13489     {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
13490     {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
13491     {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
13492     {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
13493     {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
13494     {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
13495     {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
13496     {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
13497     {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
13498     {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13499     {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13500     {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
13501     {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
13502     {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
13503     {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
13504     {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
13505     {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
13506     {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
13511     {"bits": [0, 3], "name": "ER_TRI"},
13512     {"bits": [4, 7], "name": "ER_POINT"},
13513     {"bits": [8, 11], "name": "ER_RECT"},
13514     {"bits": [12, 17], "name": "ER_LINE_LR"},
13515     {"bits": [18, 23], "name": "ER_LINE_RL"},
13516     {"bits": [24, 27], "name": "ER_LINE_TB"},
13517     {"bits": [28, 31], "name": "ER_LINE_BT"}
13522     {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
13523     {"bits": [10, 10], "name": "LAST_PIXEL"},
13524     {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
13525     {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
13526     {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
13531     {"bits": [0, 15], "name": "LINE_PATTERN"},
13532     {"bits": [16, 23], "name": "REPEAT_COUNT"},
13533     {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
13534     {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
13539     {"bits": [0, 3], "name": "CURRENT_PTR"},
13540     {"bits": [8, 15], "name": "CURRENT_COUNT"}
13545     {"bits": [0, 0], "name": "MSAA_ENABLE"},
13546     {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
13547     {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
13548     {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
13549     {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
13550     {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
13555     {"bits": [0, 0], "name": "WALK_SIZE"},
13556     {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
13557     {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
13558     {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
13559     {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
13560     {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
13561     {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
13562     {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
13563     {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
13564     {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
13565     {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
13566     {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
13567     {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
13568     {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
13569     {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
13570     {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
13571     {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
13572     {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
13573     {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
13574     {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
13575     {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
13576     {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
13577     {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
13578     {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
13583     {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
13584     {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"}
13589     {"bits": [0, 13], "name": "X_COORD"}
13594     {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
13595     {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
13600     {"bits": [0, 15], "name": "COUNT"}
13605     {"bits": [0, 13], "name": "Y_COORD"}
13610     {"bits": [0, 9], "name": "PERF_SEL"}
13615     {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
13616     {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
13617     {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
13618     {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
13619     {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
13620     {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
13621     {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
13622     {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
13623     {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
13624     {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
13625     {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
13626     {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
13627     {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
13628     {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
13629     {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
13634     {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
13635     {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
13636     {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
13641     {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
13642     {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
13647     {"bits": [0, 15], "name": "X"},
13648     {"bits": [16, 31], "name": "Y"}
13653     {"bits": [0, 15], "name": "BR_X"},
13654     {"bits": [16, 31], "name": "BR_Y"}
13659     {"bits": [0, 15], "name": "TL_X"},
13660     {"bits": [16, 31], "name": "TL_Y"}
13665     {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
13666     {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
13667     {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
13668     {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"}
13673     {"bits": [0, 0], "name": "ENABLE"},
13674     {"bits": [1, 2], "name": "NUM_SE"},
13675     {"bits": [5, 6], "name": "NUM_RB_PER_SE"},
13676     {"bits": [12, 13], "name": "NUM_SC"},
13677     {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
13678     {"bits": [20, 21], "name": "NUM_PACKER_PER_SC"}
13683     {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
13684     {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
13689     {"bits": [0, 14], "name": "BR_X"},
13690     {"bits": [16, 30], "name": "BR_Y"}
13695     {"bits": [0, 14], "name": "TL_X"},
13696     {"bits": [16, 30], "name": "TL_Y"},
13697     {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
13702     {"bits": [1, 4], "name": "STEREO_MODE"},
13703     {"bits": [5, 7], "name": "RT_SLICE_MODE"},
13704     {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
13705     {"bits": [16, 18], "name": "VP_ID_MODE"},
13706     {"bits": [19, 22], "name": "VP_ID_OFFSET"}
13711     {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
13712     {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
13717     {"bits": [0, 15], "name": "WIDTH"}
13722     {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
13723     {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
13724     {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
13725     {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
13730     {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
13735     {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
13736     {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
13737     {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
13738     {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
13739     {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
13744     {"bits": [0, 9], "name": "PERF_SEL"},
13745     {"bits": [10, 19], "name": "PERF_SEL1"},
13746     {"bits": [20, 23], "name": "CNTR_MODE"},
13747     {"bits": [24, 27], "name": "PERF_MODE1"},
13748     {"bits": [28, 31], "name": "PERF_MODE"}
13753     {"bits": [0, 9], "name": "PERF_SEL2"},
13754     {"bits": [10, 19], "name": "PERF_SEL3"},
13755     {"bits": [24, 27], "name": "PERF_MODE3"},
13756     {"bits": [28, 31], "name": "PERF_MODE2"}
13761     {"bits": [0, 15], "name": "MIN_SIZE"},
13762     {"bits": [16, 31], "name": "MAX_SIZE"}
13767     {"bits": [0, 15], "name": "HEIGHT"},
13768     {"bits": [16, 31], "name": "WIDTH"}
13773     {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
13774     {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
13779     {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
13780     {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
13781     {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
13782     {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
13783     {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
13784     {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
13785     {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
13786     {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
13787     {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
13788     {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
13789     {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
13794     {"bits": [0, 0], "name": "CULL_FRONT"},
13795     {"bits": [1, 1], "name": "CULL_BACK"},
13796     {"bits": [2, 2], "name": "FACE"},
13797     {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
13798     {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
13799     {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
13800     {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
13801     {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
13802     {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
13803     {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
13804     {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
13805     {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
13806     {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
13807     {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
13808     {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
13809     {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
13814     {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
13815     {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
13816     {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
13817     {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
13818     {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}
13823     {"bits": [0, 0], "name": "PIX_CENTER"},
13824     {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
13825     {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
13830     {"bits": [0, 3], "name": "FEATURE_SEL"},
13831     {"bits": [4, 7], "name": "SE_INDEX"},
13832     {"bits": [8, 11], "name": "SA_INDEX"},
13833     {"bits": [12, 15], "name": "WGP_INDEX"},
13834     {"bits": [16, 17], "name": "EVENT_SEL"},
13835     {"bits": [18, 19], "name": "UNUSED"},
13836     {"bits": [20, 20], "name": "ENABLE"},
13837     {"bits": [21, 31], "name": "RESERVED"}
13842     {"bits": [0, 0], "name": "ENABLE"},
13843     {"bits": [1, 1], "name": "MODE_SELECT"},
13844     {"bits": [2, 2], "name": "RESET"},
13845     {"bits": [3, 31], "name": "RESERVED"}
13850     {"bits": [0, 3], "name": "VFID"},
13851     {"bits": [4, 5], "name": "CNT_ID"},
13852     {"bits": [6, 31], "name": "RESERVED"}
13857     {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
13862     {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
13867     {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
13868     {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
13873     {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
13874     {"bits": [1, 1], "name": "StrobeStartAccumulation"},
13875     {"bits": [2, 2], "name": "StrobeRearmAccum"},
13876     {"bits": [3, 3], "name": "StrobeResetSpmBlock"},
13877     {"bits": [4, 7], "name": "StrobeStartSpm"},
13878     {"bits": [8, 8], "name": "StrobeRearmSwaAccum"},
13879     {"bits": [9, 9], "name": "StrobeStartSwa"},
13880     {"bits": [10, 10], "name": "StrobePerfmonSampleWires"},
13881     {"bits": [11, 31], "name": "RESERVED"}
13886     {"bits": [0, 10], "name": "addr"},
13887     {"bits": [11, 31], "name": "RESERVED"}
13892     {"bits": [0, 7], "name": "global_offset"},
13893     {"bits": [8, 15], "name": "spmwithaccum_se_offset"},
13894     {"bits": [16, 23], "name": "spmwithaccum_global_offset"},
13895     {"bits": [24, 31], "name": "RESERVED"}
13900     {"bits": [0, 7], "name": "data"},
13901     {"bits": [8, 31], "name": "RESERVED"}
13906     {"bits": [0, 7], "name": "spp_addr_region"},
13907     {"bits": [8, 15], "name": "swa_addr_region"},
13908     {"bits": [16, 31], "name": "RESERVED"}
13913     {"bits": [0, 6], "name": "addr"},
13914     {"bits": [7, 31], "name": "RESERVED"}
13919     {"bits": [0, 18], "name": "DataRamWrCount"},
13920     {"bits": [19, 31], "name": "RESERVED"}
13925     {"bits": [0, 0], "name": "EnableAccum"},
13926     {"bits": [1, 1], "name": "EnableSpmWithAccumMode"},
13927     {"bits": [2, 2], "name": "EnableSPPMode"},
13928     {"bits": [3, 3], "name": "AutoResetPerfmonDisable"},
13929     {"bits": [4, 4], "name": "SwaAutoResetPerfmonDisable"},
13930     {"bits": [5, 5], "name": "AutoAccumEn"},
13931     {"bits": [6, 6], "name": "SwaAutoAccumEn"},
13932     {"bits": [7, 7], "name": "AutoSpmEn"},
13933     {"bits": [8, 8], "name": "SwaAutoSpmEn"},
13934     {"bits": [9, 9], "name": "Globals_LoadOverride"},
13935     {"bits": [10, 10], "name": "Globals_SwaLoadOverride"},
13936     {"bits": [11, 11], "name": "SE0_LoadOverride"},
13937     {"bits": [12, 12], "name": "SE0_SwaLoadOverride"},
13938     {"bits": [13, 13], "name": "SE1_LoadOverride"},
13939     {"bits": [14, 14], "name": "SE1_SwaLoadOverride"},
13940     {"bits": [15, 15], "name": "SE2_LoadOverride"},
13941     {"bits": [16, 16], "name": "SE2_SwaLoadOverride"},
13942     {"bits": [17, 17], "name": "SE3_LoadOverride"},
13943     {"bits": [18, 18], "name": "SE3_SwaLoadOverride"}
13948     {"bits": [0, 7], "name": "SamplesRequested"}
13953     {"bits": [0, 7], "name": "NumbSamplesCompleted"},
13954     {"bits": [8, 8], "name": "AccumDone"},
13955     {"bits": [9, 9], "name": "SpmDone"},
13956     {"bits": [10, 10], "name": "AccumOverflow"},
13957     {"bits": [11, 11], "name": "AccumArmed"},
13958     {"bits": [12, 12], "name": "SequenceInProgress"},
13959     {"bits": [13, 13], "name": "FinalSequenceInProgress"},
13960     {"bits": [14, 14], "name": "AllFifosEmpty"},
13961     {"bits": [15, 15], "name": "FSMIsIdle"},
13962     {"bits": [16, 16], "name": "SwaAccumDone"},
13963     {"bits": [17, 17], "name": "SwaSpmDone"},
13964     {"bits": [18, 18], "name": "SwaAccumOverflow"},
13965     {"bits": [19, 19], "name": "SwaAccumArmed"},
13966     {"bits": [20, 20], "name": "AllSegsDone"},
13967     {"bits": [21, 21], "name": "RearmSwaPending"},
13968     {"bits": [22, 22], "name": "RearmSppPending"},
13969     {"bits": [23, 31], "name": "RESERVED"}
13974     {"bits": [0, 15], "name": "Threshold"}
13979     {"bits": [0, 6], "name": "DESER_START_SKEW"},
13980     {"bits": [7, 31], "name": "RESERVED"}
13985     {"bits": [0, 6], "name": "data"},
13986     {"bits": [7, 31], "name": "RESERVED"}
13991     {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"},
13992     {"bits": [7, 31], "name": "RESERVED"}
13997     {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"},
13998     {"bits": [7, 31], "name": "RESERVED"}
14003     {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"},
14004     {"bits": [8, 31], "name": "RESERVED"}
14009     {"bits": [0, 15], "name": "OFFSET"},
14010     {"bits": [16, 31], "name": "RESERVED"}
14015     {"bits": [0, 11], "name": "RESERVED1"},
14016     {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
14017     {"bits": [14, 15], "name": "RESERVED"},
14018     {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
14023     {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14024     {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"},
14025     {"bits": [16, 31], "name": "RESERVED"}
14030     {"bits": [0, 15], "name": "RING_BASE_HI"},
14031     {"bits": [16, 31], "name": "RESERVED"}
14036     {"bits": [0, 7], "name": "SE0_NUM_LINE"},
14037     {"bits": [8, 15], "name": "SE1_NUM_LINE"},
14038     {"bits": [16, 23], "name": "SE2_NUM_LINE"},
14039     {"bits": [24, 31], "name": "SE3_NUM_LINE"}
14044     {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14045     {"bits": [8, 10], "name": "RESERVED1"},
14046     {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
14047     {"bits": [16, 20], "name": "SE0_NUM_LINE"},
14048     {"bits": [21, 25], "name": "SE1_NUM_LINE"},
14049     {"bits": [26, 30], "name": "SE2_NUM_LINE"},
14050     {"bits": [31, 31], "name": "RESERVED"}
14055     {"bits": [0, 4], "name": "RESERVED"},
14056     {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
14061     {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
14062     {"bits": [8, 31], "name": "RESERVED"}
14067     {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"},
14068     {"bits": [9, 31], "name": "RESERVED"}
14073     {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"},
14074     {"bits": [7, 31], "name": "RESERVED"}
14079     {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"},
14080     {"bits": [7, 31], "name": "RESERVED"}
14085     {"bits": [0, 0], "name": "PauseSpmSamplingRequest"}
14090     {"bits": [0, 0], "name": "SpmSamplingPaused"}
14095     {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
14096     {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
14097     {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
14098     {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
14099     {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
14100     {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
14101     {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
14102     {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
14103     {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
14104     {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
14109     {"bits": [0, 23], "name": "IMMED"},
14110     {"bits": [24, 26], "name": "ID"},
14111     {"bits": [27, 27], "name": "reserved27"},
14112     {"bits": [28, 30], "name": "OP"},
14113     {"bits": [31, 31], "name": "reserved31"}
14118     {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
14119     {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
14124     {"bits": [0, 15], "name": "CMD_OP"}
14129     {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
14130     {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
14131     {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
14132     {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
14133     {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
14134     {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
14135     {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
14140     {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
14141     {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
14142     {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
14143     {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
14144     {"bits": [26, 26], "name": "FORCE_HALF_RATE_PC_EXP"},
14145     {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
14146     {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
14147     {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
14148     {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
14153     {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
14154     {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
14155     {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
14156     {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
14157     {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
14158     {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
14159     {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
14164     {"bits": [0, 3], "name": "BIN0_MIN"},
14165     {"bits": [4, 7], "name": "BIN0_MAX"},
14166     {"bits": [8, 11], "name": "BIN1_MIN"},
14167     {"bits": [12, 15], "name": "BIN1_MAX"},
14168     {"bits": [16, 19], "name": "BIN2_MIN"},
14169     {"bits": [20, 23], "name": "BIN2_MAX"},
14170     {"bits": [24, 27], "name": "BIN3_MIN"},
14171     {"bits": [28, 31], "name": "BIN3_MAX"}
14176     {"bits": [0, 5], "name": "OFFSET"},
14177     {"bits": [8, 9], "name": "DEFAULT_VAL"},
14178     {"bits": [10, 10], "name": "FLAT_SHADE"},
14179     {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
14180     {"bits": [13, 16], "name": "CYL_WRAP"},
14181     {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
14182     {"bits": [18, 18], "name": "DUP"},
14183     {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14184     {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14185     {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14186     {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
14187     {"bits": [24, 24], "name": "ATTR0_VALID"},
14188     {"bits": [25, 25], "name": "ATTR1_VALID"}
14193     {"bits": [0, 5], "name": "OFFSET"},
14194     {"bits": [8, 9], "name": "DEFAULT_VAL"},
14195     {"bits": [10, 10], "name": "FLAT_SHADE"},
14196     {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
14197     {"bits": [18, 18], "name": "DUP"},
14198     {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14199     {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14200     {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14201     {"bits": [24, 24], "name": "ATTR0_VALID"},
14202     {"bits": [25, 25], "name": "ATTR1_VALID"}
14207     {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
14208     {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
14209     {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
14210     {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
14211     {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
14212     {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
14213     {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
14214     {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
14215     {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
14216     {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
14217     {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
14218     {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
14219     {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
14220     {"bits": [13, 13], "name": "ANCILLARY_ENA"},
14221     {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
14222     {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
14227     {"bits": [0, 5], "name": "NUM_INTERP"},
14228     {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
14229     {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
14230     {"bits": [9, 13], "name": "NUM_PRIM_INTERP"},
14231     {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
14232     {"bits": [15, 15], "name": "PS_W32_EN"}
14237     {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
14238     {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
14239     {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
14240     {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
14241     {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
14242     {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
14243     {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
14244     {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
14249     {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
14254     {"bits": [0, 5], "name": "LIMIT"}
14259     {"bits": [0, 7], "name": "MEM_BASE"}
14264     {"bits": [0, 5], "name": "VGPRS"},
14265     {"bits": [6, 9], "name": "SGPRS"},
14266     {"bits": [10, 11], "name": "PRIORITY"},
14267     {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14268     {"bits": [20, 20], "name": "PRIV"},
14269     {"bits": [21, 21], "name": "DX10_CLAMP"},
14270     {"bits": [23, 23], "name": "IEEE_MODE"},
14271     {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
14272     {"bits": [25, 25], "name": "MEM_ORDERED"},
14273     {"bits": [26, 26], "name": "FWD_PROGRESS"},
14274     {"bits": [27, 27], "name": "WGP_MODE"},
14275     {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
14276     {"bits": [31, 31], "name": "FP16_OVFL"}
14281     {"bits": [0, 5], "name": "VGPRS"},
14282     {"bits": [6, 9], "name": "SGPRS"},
14283     {"bits": [10, 11], "name": "PRIORITY"},
14284     {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14285     {"bits": [20, 20], "name": "PRIV"},
14286     {"bits": [21, 21], "name": "DX10_CLAMP"},
14287     {"bits": [23, 23], "name": "IEEE_MODE"},
14288     {"bits": [24, 24], "name": "MEM_ORDERED"},
14289     {"bits": [25, 25], "name": "FWD_PROGRESS"},
14290     {"bits": [26, 26], "name": "WGP_MODE"},
14291     {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
14292     {"bits": [30, 30], "name": "FP16_OVFL"}
14297     {"bits": [0, 5], "name": "VGPRS"},
14298     {"bits": [6, 9], "name": "SGPRS"},
14299     {"bits": [10, 11], "name": "PRIORITY"},
14300     {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14301     {"bits": [20, 20], "name": "PRIV"},
14302     {"bits": [21, 21], "name": "DX10_CLAMP"},
14303     {"bits": [23, 23], "name": "IEEE_MODE"},
14304     {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
14305     {"bits": [25, 25], "name": "MEM_ORDERED"},
14306     {"bits": [26, 26], "name": "FWD_PROGRESS"},
14307     {"bits": [27, 27], "name": "LOAD_PROVOKING_VTX"},
14308     {"bits": [29, 29], "name": "FP16_OVFL"}
14313     {"bits": [0, 5], "name": "VGPRS"},
14314     {"bits": [6, 9], "name": "SGPRS"},
14315     {"bits": [10, 11], "name": "PRIORITY"},
14316     {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14317     {"bits": [20, 20], "name": "PRIV"},
14318     {"bits": [21, 21], "name": "DX10_CLAMP"},
14319     {"bits": [23, 23], "name": "IEEE_MODE"},
14320     {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14321     {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
14322     {"bits": [27, 27], "name": "MEM_ORDERED"},
14323     {"bits": [28, 28], "name": "FWD_PROGRESS"},
14324     {"bits": [31, 31], "name": "FP16_OVFL"}
14329     {"bits": [0, 0], "name": "SCRATCH_EN"},
14330     {"bits": [1, 5], "name": "USER_SGPR"},
14331     {"bits": [6, 6], "name": "TRAP_PRESENT"},
14332     {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14333     {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
14334     {"bits": [18, 18], "name": "OC_LDS_EN"},
14335     {"bits": [19, 26], "name": "LDS_SIZE"},
14336     {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14337     {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14342     {"bits": [0, 0], "name": "SCRATCH_EN"},
14343     {"bits": [1, 5], "name": "USER_SGPR"},
14344     {"bits": [6, 6], "name": "TRAP_PRESENT"},
14345     {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14346     {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
14347     {"bits": [18, 18], "name": "OC_LDS_EN"},
14348     {"bits": [19, 26], "name": "LDS_SIZE"},
14349     {"bits": [27, 27], "name": "SKIP_USGPR0"},
14350     {"bits": [28, 28], "name": "USER_SGPR_MSB"}
14355     {"bits": [0, 0], "name": "SCRATCH_EN"},
14356     {"bits": [1, 5], "name": "USER_SGPR"},
14357     {"bits": [6, 6], "name": "TRAP_PRESENT"},
14358     {"bits": [7, 7], "name": "OC_LDS_EN"},
14359     {"bits": [8, 8], "name": "TG_SIZE_EN"},
14360     {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14361     {"bits": [18, 26], "name": "LDS_SIZE"},
14362     {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14363     {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14368     {"bits": [0, 0], "name": "SCRATCH_EN"},
14369     {"bits": [1, 5], "name": "USER_SGPR"},
14370     {"bits": [6, 6], "name": "TRAP_PRESENT"},
14371     {"bits": [7, 7], "name": "WAVE_CNT_EN"},
14372     {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
14373     {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14374     {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
14375     {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
14376     {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14377     {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14382     {"bits": [0, 0], "name": "SCRATCH_EN"},
14383     {"bits": [1, 5], "name": "USER_SGPR"},
14384     {"bits": [6, 6], "name": "TRAP_PRESENT"},
14385     {"bits": [7, 7], "name": "OC_LDS_EN"},
14386     {"bits": [8, 8], "name": "SO_BASE0_EN"},
14387     {"bits": [9, 9], "name": "SO_BASE1_EN"},
14388     {"bits": [10, 10], "name": "SO_BASE2_EN"},
14389     {"bits": [11, 11], "name": "SO_BASE3_EN"},
14390     {"bits": [12, 12], "name": "SO_EN"},
14391     {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14392     {"bits": [22, 22], "name": "PC_BASE_EN"},
14393     {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
14394     {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14395     {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14400     {"bits": [0, 15], "name": "CU_EN"},
14401     {"bits": [16, 21], "name": "WAVE_LIMIT"},
14402     {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
14403     {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
14408     {"bits": [0, 5], "name": "WAVE_LIMIT"},
14409     {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
14410     {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
14411     {"bits": [16, 31], "name": "CU_EN"}
14416     {"bits": [0, 15], "name": "CU_EN"},
14417     {"bits": [16, 21], "name": "WAVE_LIMIT"},
14418     {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
14423     {"bits": [0, 15], "name": "CU_EN"},
14424     {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"}
14429     {"bits": [0, 15], "name": "CU_EN"}
14434     {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
14435     {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
14436     {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
14437     {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
14438     {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
14443     {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
14444     {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
14445     {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
14446     {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
14447     {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
14448     {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
14449     {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
14450     {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
14455     {"bits": [0, 6], "name": "CONTRIBUTION"}
14460     {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
14465     {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
14466     {"bits": [6, 6], "name": "VS_HALF_PACK"},
14467     {"bits": [7, 7], "name": "NO_PC_EXPORT"},
14468     {"bits": [8, 12], "name": "PRIM_EXPORT_COUNT"}
14473     {"bits": [0, 0], "name": "TARGET_INST"},
14474     {"bits": [1, 1], "name": "TARGET_DATA"},
14475     {"bits": [2, 2], "name": "INVALIDATE"},
14476     {"bits": [16, 16], "name": "COMPLETE"},
14477     {"bits": [17, 18], "name": "L2_WB_POLICY"}
14482     {"bits": [0, 8], "name": "PERF_SEL"},
14483     {"bits": [20, 23], "name": "SPM_MODE"},
14484     {"bits": [28, 31], "name": "PERF_MODE"}
14489     {"bits": [0, 0], "name": "PS_EN"},
14490     {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
14491     {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
14492     {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
14493     {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
14494     {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
14495     {"bits": [6, 6], "name": "CS_EN"},
14496     {"bits": [8, 9], "name": "CNTR_RATE"},
14497     {"bits": [13, 13], "name": "DISABLE_FLUSH"},
14498     {"bits": [14, 14], "name": "DISABLE_ME0PIPE0_PERF"},
14499     {"bits": [15, 15], "name": "DISABLE_ME0PIPE1_PERF"},
14500     {"bits": [16, 16], "name": "DISABLE_ME1PIPE0_PERF"},
14501     {"bits": [17, 17], "name": "DISABLE_ME1PIPE1_PERF"},
14502     {"bits": [18, 18], "name": "DISABLE_ME1PIPE2_PERF"},
14503     {"bits": [19, 19], "name": "DISABLE_ME1PIPE3_PERF"}
14508     {"bits": [0, 0], "name": "FORCE_EN"}
14513     {"bits": [0, 3], "name": "BASE_HI"},
14514     {"bits": [8, 29], "name": "SIZE"}
14519     {"bits": [0, 1], "name": "MODE"},
14520     {"bits": [2, 2], "name": "ALL_VMID"},
14521     {"bits": [3, 3], "name": "CH_PERF_EN"},
14522     {"bits": [4, 4], "name": "INTERRUPT_EN"},
14523     {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
14524     {"bits": [6, 8], "name": "HIWATER"},
14525     {"bits": [9, 9], "name": "REG_STALL_EN"},
14526     {"bits": [10, 10], "name": "SPI_STALL_EN"},
14527     {"bits": [11, 11], "name": "SQ_STALL_EN"},
14528     {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
14529     {"bits": [13, 13], "name": "UTIL_TIMER"},
14530     {"bits": [14, 15], "name": "WAVESTART_MODE"},
14531     {"bits": [16, 17], "name": "RT_FREQ"},
14532     {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
14533     {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
14534     {"bits": [20, 22], "name": "LOWATER_OFFSET"},
14535     {"bits": [28, 28], "name": "AUTO_FLUSH_PADDING_DIS"},
14536     {"bits": [29, 29], "name": "AUTO_FLUSH_MODE"},
14537     {"bits": [30, 30], "name": "CAPTURE_ALL"},
14538     {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
14543     {"bits": [0, 1], "name": "SIMD_SEL"},
14544     {"bits": [4, 7], "name": "WGP_SEL"},
14545     {"bits": [9, 9], "name": "SA_SEL"},
14546     {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
14551     {"bits": [0, 11], "name": "FINISH_PENDING"},
14552     {"bits": [12, 23], "name": "FINISH_DONE"},
14553     {"bits": [24, 24], "name": "UTC_ERR"},
14554     {"bits": [25, 25], "name": "BUSY"},
14555     {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
14556     {"bits": [27, 27], "name": "EVENT_CNTR_STALL"},
14557     {"bits": [28, 31], "name": "OWNER_VMID"}
14562     {"bits": [0, 0], "name": "BUF0_FULL"},
14563     {"bits": [1, 1], "name": "BUF1_FULL"},
14564     {"bits": [4, 4], "name": "PACKET_LOST_BUF_NO_LOCKDOWN"}
14569     {"bits": [0, 10], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
14570     {"bits": [12, 12], "name": "BOP_EVENTS_TOKEN_INCLUDE"},
14571     {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
14572     {"bits": [24, 25], "name": "INST_EXCLUDE"},
14573     {"bits": [26, 28], "name": "REG_EXCLUDE"},
14574     {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
14579     {"bits": [0, 28], "name": "OFFSET"},
14580     {"bits": [31, 31], "name": "BUFFER_ID"}
14585     {"bits": [0, 19], "name": "WAVE_SLOT"}
14590     {"bits": [0, 7], "name": "VGPR_BASE"},
14591     {"bits": [8, 15], "name": "VGPR_SIZE"},
14592     {"bits": [16, 23], "name": "SGPR_BASE"},
14593     {"bits": [24, 27], "name": "SGPR_SIZE"}
14598     {"bits": [0, 4], "name": "WAVE_ID"},
14599     {"bits": [8, 9], "name": "SIMD_ID"},
14600     {"bits": [10, 13], "name": "WGP_ID"},
14601     {"bits": [16, 16], "name": "SA_ID"},
14602     {"bits": [18, 19], "name": "SE_ID"}
14607     {"bits": [0, 3], "name": "QUEUE_ID"},
14608     {"bits": [4, 5], "name": "PIPE_ID"},
14609     {"bits": [8, 9], "name": "ME_ID"},
14610     {"bits": [12, 14], "name": "STATE_ID"},
14611     {"bits": [16, 20], "name": "WG_ID"},
14612     {"bits": [24, 27], "name": "VM_ID"}
14617     {"bits": [0, 3], "name": "WAVE_ID"},
14618     {"bits": [4, 5], "name": "SIMD_ID"},
14619     {"bits": [6, 7], "name": "PIPE_ID"},
14620     {"bits": [8, 11], "name": "CU_ID"},
14621     {"bits": [12, 12], "name": "SH_ID"},
14622     {"bits": [13, 14], "name": "SE_ID"},
14623     {"bits": [15, 15], "name": "WAVE_ID_MSB"},
14624     {"bits": [16, 19], "name": "TG_ID"},
14625     {"bits": [20, 23], "name": "VM_ID"},
14626     {"bits": [24, 26], "name": "QUEUE_ID"},
14627     {"bits": [27, 29], "name": "STATE_ID"},
14628     {"bits": [30, 31], "name": "ME_ID"}
14633     {"bits": [24, 24], "name": "WAVE_IDLE"},
14634     {"bits": [25, 31], "name": "MISC_CNT"}
14639     {"bits": [0, 3], "name": "VM_CNT"},
14640     {"bits": [4, 6], "name": "EXP_CNT"},
14641     {"bits": [7, 7], "name": "LGKM_CNT_BIT4"},
14642     {"bits": [8, 11], "name": "LGKM_CNT"},
14643     {"bits": [12, 14], "name": "VALU_CNT"},
14644     {"bits": [22, 23], "name": "VM_CNT_HI"},
14645     {"bits": [24, 24], "name": "LGKM_CNT_BIT5"},
14646     {"bits": [26, 31], "name": "VS_CNT"}
14651     {"bits": [0, 1], "name": "INST_PREFETCH"},
14652     {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"},
14653     {"bits": [8, 9], "name": "MEM_ORDER"},
14654     {"bits": [10, 10], "name": "FWD_PROGRESS"},
14655     {"bits": [11, 11], "name": "WAVE64"}
14660     {"bits": [0, 8], "name": "LDS_BASE"},
14661     {"bits": [12, 20], "name": "LDS_SIZE"},
14662     {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
14667     {"bits": [0, 3], "name": "FP_ROUND"},
14668     {"bits": [4, 7], "name": "FP_DENORM"},
14669     {"bits": [8, 8], "name": "DX10_CLAMP"},
14670     {"bits": [9, 9], "name": "IEEE"},
14671     {"bits": [10, 10], "name": "LOD_CLAMPED"},
14672     {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14673     {"bits": [23, 23], "name": "FP16_OVFL"},
14674     {"bits": [27, 27], "name": "DISABLE_PERF"}
14679     {"bits": [0, 15], "name": "PC_HI"}
14684     {"bits": [0, 0], "name": "POPS_EN"},
14685     {"bits": [1, 2], "name": "POPS_PACKER_ID"}
14690     {"bits": [0, 1], "name": "DEP_MODE"}
14695     {"bits": [0, 19], "name": "CYCLES"}
14700     {"bits": [0, 0], "name": "SCC"},
14701     {"bits": [1, 2], "name": "SPI_PRIO"},
14702     {"bits": [3, 4], "name": "USER_PRIO"},
14703     {"bits": [5, 5], "name": "PRIV"},
14704     {"bits": [6, 6], "name": "TRAP_EN"},
14705     {"bits": [7, 7], "name": "TTRACE_EN"},
14706     {"bits": [8, 8], "name": "EXPORT_RDY"},
14707     {"bits": [9, 9], "name": "EXECZ"},
14708     {"bits": [10, 10], "name": "VCCZ"},
14709     {"bits": [11, 11], "name": "IN_TG"},
14710     {"bits": [12, 12], "name": "IN_BARRIER"},
14711     {"bits": [13, 13], "name": "HALT"},
14712     {"bits": [14, 14], "name": "TRAP"},
14713     {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
14714     {"bits": [16, 16], "name": "VALID"},
14715     {"bits": [17, 17], "name": "ECC_ERR"},
14716     {"bits": [18, 18], "name": "SKIP_EXPORT"},
14717     {"bits": [19, 19], "name": "PERF_EN"},
14718     {"bits": [23, 23], "name": "FATAL_HALT"},
14719     {"bits": [27, 27], "name": "MUST_EXPORT"}
14724     {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
14725     {"bits": [10, 10], "name": "SAVECTX"},
14726     {"bits": [11, 11], "name": "ILLEGAL_INST"},
14727     {"bits": [12, 14], "name": "EXCP_HI"},
14728     {"bits": [15, 15], "name": "BUFFER_OOB"},
14729     {"bits": [16, 19], "name": "EXCP_CYCLE"},
14730     {"bits": [20, 23], "name": "EXCP_GROUP_MASK"},
14731     {"bits": [24, 24], "name": "EXCP_WAVE64HI"},
14732     {"bits": [28, 28], "name": "UTC_ERROR"},
14733     {"bits": [29, 31], "name": "DP_RATE"}
14738     {"bits": [0, 5], "name": "SRC0"},
14739     {"bits": [6, 11], "name": "SRC1"},
14740     {"bits": [12, 17], "name": "SRC2"},
14741     {"bits": [18, 23], "name": "DST"}
14746     {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
14747     {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
14748     {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
14749     {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
14750     {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
14751     {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
14752     {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
14753     {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
14754     {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
14755     {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
14756     {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
14757     {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
14758     {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
14759     {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
14760     {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
14761     {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
14762     {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
14767     {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
14768     {"bits": [4, 7], "name": "MRT1_EPSILON"},
14769     {"bits": [8, 11], "name": "MRT2_EPSILON"},
14770     {"bits": [12, 15], "name": "MRT3_EPSILON"},
14771     {"bits": [16, 19], "name": "MRT4_EPSILON"},
14772     {"bits": [20, 23], "name": "MRT5_EPSILON"},
14773     {"bits": [24, 27], "name": "MRT6_EPSILON"},
14774     {"bits": [28, 31], "name": "MRT7_EPSILON"}
14779     {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
14780     {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
14781     {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
14782     {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
14783     {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
14784     {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
14789     {"bits": [0, 9], "name": "PERF_SEL"},
14790     {"bits": [20, 23], "name": "CNTR_MODE"},
14791     {"bits": [28, 31], "name": "PERF_MODE"}
14796     {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
14797     {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
14798     {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
14799     {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
14800     {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
14801     {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
14802     {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
14803     {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
14808     {"bits": [0, 0], "name": "MRT0_FMT_MAPPING_DISABLE"},
14809     {"bits": [1, 1], "name": "MRT1_FMT_MAPPING_DISABLE"},
14810     {"bits": [2, 2], "name": "MRT2_FMT_MAPPING_DISABLE"},
14811     {"bits": [3, 3], "name": "MRT3_FMT_MAPPING_DISABLE"},
14812     {"bits": [4, 4], "name": "MRT4_FMT_MAPPING_DISABLE"},
14813     {"bits": [5, 5], "name": "MRT5_FMT_MAPPING_DISABLE"},
14814     {"bits": [6, 6], "name": "MRT6_FMT_MAPPING_DISABLE"},
14815     {"bits": [7, 7], "name": "MRT7_FMT_MAPPING_DISABLE"}
14820     {"bits": [0, 7], "name": "ADDRESS"}
14825     {"bits": [0, 9], "name": "PERF_SEL"},
14826     {"bits": [28, 31], "name": "COUNTER_MODE"}
14831     {"bits": [0, 15], "name": "BASE_ADDR"}
14836     {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
14837     {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
14838     {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
14839     {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
14840     {"bits": [8, 8], "name": "ATC"},
14841     {"bits": [9, 9], "name": "NOT_EOP"},
14842     {"bits": [10, 10], "name": "REQ_PATH"},
14843     {"bits": [11, 13], "name": "MTYPE"},
14844     {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
14849     {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
14850     {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
14851     {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
14852     {"bits": [5, 5], "name": "NOT_EOP"},
14853     {"bits": [6, 6], "name": "USE_OPAQUE"},
14854     {"bits": [29, 31], "name": "REG_RT_INDEX"}
14859     {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
14860     {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
14861     {"bits": [4, 4], "name": "EN_DRAW_VP"},
14862     {"bits": [6, 6], "name": "EN_VRS_RATE"}
14867     {"bits": [0, 14], "name": "ITEMSIZE"}
14872     {"bits": [0, 10], "name": "ES_PER_GS"}
14877     {"bits": [0, 27], "name": "ADDRESS_LOW"}
14882     {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
14883     {"bits": [10, 26], "name": "ADDRESS_HI"},
14884     {"bits": [27, 27], "name": "EXTENDED_EVENT"}
14889     {"bits": [0, 3], "name": "DECR"}
14894     {"bits": [0, 3], "name": "FIRST_DECR"}
14899     {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
14900     {"bits": [14, 14], "name": "RETAIN_ORDER"},
14901     {"bits": [15, 15], "name": "RETAIN_QUADS"},
14902     {"bits": [16, 18], "name": "PRIM_ORDER"}
14907     {"bits": [0, 0], "name": "COMP_X_EN"},
14908     {"bits": [1, 1], "name": "COMP_Y_EN"},
14909     {"bits": [2, 2], "name": "COMP_Z_EN"},
14910     {"bits": [3, 3], "name": "COMP_W_EN"},
14911     {"bits": [8, 15], "name": "STRIDE"},
14912     {"bits": [16, 23], "name": "SHIFT"}
14917     {"bits": [0, 3], "name": "X_CONV"},
14918     {"bits": [4, 7], "name": "X_OFFSET"},
14919     {"bits": [8, 11], "name": "Y_CONV"},
14920     {"bits": [12, 15], "name": "Y_OFFSET"},
14921     {"bits": [16, 19], "name": "Z_CONV"},
14922     {"bits": [20, 23], "name": "Z_OFFSET"},
14923     {"bits": [24, 27], "name": "W_CONV"},
14924     {"bits": [28, 31], "name": "W_OFFSET"}
14929     {"bits": [0, 14], "name": "OFFSET"}
14934     {"bits": [0, 0], "name": "ENABLE"},
14935     {"bits": [2, 8], "name": "CNT"},
14936     {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
14941     {"bits": [0, 10], "name": "MAX_VERT_OUT"}
14946     {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
14947     {"bits": [3, 3], "name": "RESERVED_0"},
14948     {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
14949     {"bits": [6, 10], "name": "RESERVED_1"},
14950     {"bits": [11, 11], "name": "GS_C_PACK_EN"},
14951     {"bits": [12, 12], "name": "RESERVED_2"},
14952     {"bits": [13, 13], "name": "ES_PASSTHRU"},
14953     {"bits": [14, 14], "name": "COMPUTE_MODE"},
14954     {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
14955     {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
14956     {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
14957     {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
14958     {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
14959     {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
14960     {"bits": [21, 22], "name": "ONCHIP"}
14965     {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
14966     {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
14967     {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
14972     {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
14973     {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
14974     {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
14975     {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
14976     {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
14981     {"bits": [0, 10], "name": "GS_PER_ES"}
14986     {"bits": [0, 3], "name": "GS_PER_VS"}
14991     {"bits": [0, 1], "name": "TESS_MODE"}
14996     {"bits": [0, 7], "name": "REUSE_DEPTH"}
15001     {"bits": [0, 9], "name": "OFFCHIP_BUFFERING"},
15002     {"bits": [10, 11], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
15007     {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
15008     {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
15013     {"bits": [0, 7], "name": "NUM_PATCHES"},
15014     {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
15015     {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
15020     {"bits": [0, 0], "name": "RESET_EN"},
15021     {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
15026     {"bits": [0, 2], "name": "PATH_SELECT"}
15031     {"bits": [0, 6], "name": "DEALLOC_DIST"}
15036     {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
15037     {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
15038     {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
15043     {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
15048     {"bits": [0, 0], "name": "REUSE_OFF"}
15053     {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
15054     {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
15055     {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
15056     {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
15057     {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
15058     {"bits": [8, 8], "name": "DYNAMIC_HS"},
15059     {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
15060     {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
15061     {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
15062     {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
15063     {"bits": [13, 13], "name": "PRIMGEN_EN"},
15064     {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
15065     {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
15066     {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
15067     {"bits": [21, 21], "name": "HS_W32_EN"},
15068     {"bits": [22, 22], "name": "GS_W32_EN"},
15069     {"bits": [23, 23], "name": "VS_W32_EN"},
15070     {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
15071     {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"},
15072     {"bits": [26, 26], "name": "PRIMGEN_PASSTHRU_NO_MSG"}
15077     {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
15078     {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
15079     {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
15080     {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
15085     {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
15086     {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
15087     {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
15088     {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
15089     {"bits": [4, 6], "name": "RAST_STREAM"},
15090     {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
15091     {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
15092     {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
15097     {"bits": [0, 8], "name": "VERTEX_STRIDE"}
15102     {"bits": [0, 9], "name": "STRIDE"}
15107     {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
15108     {"bits": [8, 15], "name": "ACCUM_TRI"},
15109     {"bits": [16, 23], "name": "ACCUM_QUAD"},
15110     {"bits": [24, 28], "name": "DONUT_SPLIT"},
15111     {"bits": [29, 31], "name": "TRAP_SPLIT"}
15116     {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
15117     {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
15118     {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
15119     {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
15120     {"bits": [9, 9], "name": "DEPRECATED"},
15121     {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
15122     {"bits": [14, 14], "name": "DISABLE_DONUTS"},
15123     {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15124     {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
15125     {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
15126     {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
15127     {"bits": [23, 25], "name": "MTYPE"}
15132     {"bits": [0, 15], "name": "SIZE"}
15137     {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
15142     {"bits": [0, 0], "name": "VTX_CNT_EN"}