Lines Matching refs:name
5 {"name": "INCREMENT", "value": 0},
6 {"name": "NO_INCREMENT", "value": 1}
11 {"name": "MEMORY", "value": 0},
12 {"name": "REGISTER", "value": 1}
17 {"name": "NONE", "value": 0},
18 {"name": "8_IN_16", "value": 1},
19 {"name": "8_IN_32", "value": 2},
20 {"name": "8_IN_64", "value": 3}
25 {"name": "MEM_MAPPED_REGISTER", "value": 0},
26 {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
27 {"name": "TC_L2", "value": 2},
28 {"name": "GDS", "value": 3},
29 {"name": "RESERVED", "value": 4}
34 {"name": "MEM_MAPPED_REGISTER", "value": 0},
35 {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
36 {"name": "TC_L2", "value": 2},
37 {"name": "GDS", "value": 3},
38 {"name": "RESERVED", "value": 4},
39 {"name": "MEM", "value": 5}
44 {"name": "ME", "value": 0},
45 {"name": "PFP", "value": 1},
46 {"name": "CE", "value": 2},
47 {"name": "DE", "value": 3}
52 {"name": "DST_ADDR", "value": 0},
53 {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1}
58 {"name": "DST_ADDR", "value": 0},
59 {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
60 {"name": "DST_ADDR_TC_L2", "value": 3}
65 {"name": "DST_ADDR", "value": 0},
66 {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
67 {"name": "NOWHERE", "value": 2},
68 {"name": "DST_ADDR_TC_L2", "value": 3}
73 {"name": "ME", "value": 0},
74 {"name": "PFP", "value": 1}
79 {"name": "SRC_ADDR", "value": 0},
80 {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
81 {"name": "DATA", "value": 2}
86 {"name": "SRC_ADDR", "value": 0},
87 {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
88 {"name": "DATA", "value": 2},
89 {"name": "SRC_ADDR_TC_L2", "value": 3}
94 {"name": "GL1_ALL", "value": 0},
95 {"name": "GL1_RANGE", "value": 2},
96 {"name": "GL1_FIRST_LAST", "value": 3}
101 {"name": "GL2_ALL", "value": 0},
102 {"name": "GL2_VOL", "value": 1},
103 {"name": "GL2_RANGE", "value": 2},
104 {"name": "GL2_FIRST_LAST", "value": 3}
109 {"name": "GLI_NOP", "value": 0},
110 {"name": "GLI_ALL", "value": 1},
111 {"name": "GLI_RANGE", "value": 2},
112 {"name": "GLI_FIRST_LAST", "value": 3}
117 {"name": "SEQ_PARALLEL", "value": 0},
118 {"name": "SEQ_FORWARD", "value": 1},
119 {"name": "SEQ_REVERSE", "value": 2}
128 "name": "COMMAND",
134 "name": "COMMAND",
140 "name": "CONTROL",
146 "name": "CONTROL",
152 "name": "CP_DMA_WORD0",
158 "name": "CP_DMA_WORD1",
164 "name": "CP_DMA_WORD1",
170 "name": "CP_DMA_WORD1",
176 "name": "CP_DMA_WORD2",
182 "name": "CP_DMA_WORD3",
188 "name": "DMA_DATA_WORD0",
194 "name": "DMA_DATA_WORD0",
200 "name": "DMA_DATA_WORD0",
206 "name": "DST_ADDR_HI"
211 "name": "DST_ADDR_HI"
216 "name": "DST_ADDR_LO"
221 "name": "DST_ADDR_LO"
226 "name": "GCR_CNTL",
232 "name": "IB_BASE_HI"
237 "name": "IB_BASE_LO"
242 "name": "IB_CONTROL",
248 "name": "RELEASE_MEM_OP",
254 "name": "SRC_ADDR_HI"
259 "name": "SRC_ADDR_LO"
265 {"bits": [0, 20], "name": "BYTE_COUNT"},
266 {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"},
267 {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"},
268 {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"},
269 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
270 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
271 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
272 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
273 {"bits": [30, 30], "name": "RAW_WAIT"}
278 {"bits": [0, 25], "name": "BYTE_COUNT"},
279 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
280 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
281 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
282 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
283 {"bits": [30, 30], "name": "RAW_WAIT"},
284 {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"}
289 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"},
290 {"bits": [16, 16], "name": "WR_ONE_ADDR"},
291 {"bits": [20, 20], "name": "WR_CONFIRM"},
292 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
297 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"},
298 {"bits": [16, 16], "name": "WR_ONE_ADDR"},
299 {"bits": [20, 20], "name": "WR_CONFIRM"},
300 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
305 {"bits": [0, 31], "name": "SRC_ADDR_LO"}
310 {"bits": [0, 15], "name": "SRC_ADDR_HI"},
311 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
312 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
313 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
314 {"bits": [31, 31], "name": "CP_SYNC"}
319 {"bits": [0, 15], "name": "SRC_ADDR_HI"},
320 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
321 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
322 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
323 {"bits": [31, 31], "name": "CP_SYNC"}
328 {"bits": [0, 15], "name": "SRC_ADDR_HI"},
329 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
330 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
331 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
332 {"bits": [31, 31], "name": "CP_SYNC"}
337 {"bits": [0, 31], "name": "DST_ADDR_LO"}
342 {"bits": [0, 15], "name": "DST_ADDR_HI"}
347 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
348 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
349 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
350 {"bits": [31, 31], "name": "CP_SYNC"}
355 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
356 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
357 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
358 {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
359 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
360 {"bits": [31, 31], "name": "CP_SYNC"}
365 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
366 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
367 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
368 {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
369 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
370 {"bits": [31, 31], "name": "CP_SYNC"}
375 {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"},
376 {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"},
377 {"bits": [4, 4], "name": "GLM_WB"},
378 {"bits": [5, 5], "name": "GLM_INV"},
379 {"bits": [6, 6], "name": "GLK_WB"},
380 {"bits": [7, 7], "name": "GLK_INV"},
381 {"bits": [8, 8], "name": "GLV_INV"},
382 {"bits": [9, 9], "name": "GL1_INV"},
383 {"bits": [10, 10], "name": "GL2_US"},
384 {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
385 {"bits": [13, 13], "name": "GL2_DISCARD"},
386 {"bits": [14, 14], "name": "GL2_INV"},
387 {"bits": [15, 15], "name": "GL2_WB"},
388 {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
389 {"bits": [18, 18], "name": "RANGE_IS_PA"}
394 {"bits": [0, 19], "name": "IB_SIZE"},
395 {"bits": [20, 20], "name": "CHAIN"},
396 {"bits": [23, 23], "name": "VALID"}
401 {"bits": [0, 5], "name": "EVENT_TYPE"},
402 {"bits": [8, 11], "name": "EVENT_INDEX"},
403 {"bits": [12, 12], "name": "GLM_WB"},
404 {"bits": [13, 13], "name": "GLM_INV"},
405 {"bits": [14, 14], "name": "GLV_INV"},
406 {"bits": [15, 15], "name": "GL1_INV"},
407 {"bits": [16, 16], "name": "GL2_US"},
408 {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
409 {"bits": [19, 19], "name": "GL2_DISCARD"},
410 {"bits": [20, 20], "name": "GL2_INV"},
411 {"bits": [21, 21], "name": "GL2_WB"},
412 {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}