Lines Matching defs:xs
396 tu_xs_get_immediates_packet_size_dwords(const struct ir3_shader_variant *xs)
398 const struct ir3_const_state *const_state = ir3_const_state(xs);
405 size = MIN2(size + base, xs->constlen) - base;
415 tu_xs_get_additional_cs_size_dwords(const struct ir3_shader_variant *xs)
417 uint32_t size = tu_xs_get_immediates_packet_size_dwords(xs);
423 gl_shader_stage stage, /* xs->type, but xs may be NULL */
424 const struct ir3_shader_variant *xs)
428 if (!xs) {
440 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
441 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
442 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
443 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
444 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
445 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
448 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
454 gl_shader_stage stage, /* xs->type, but xs may be NULL */
455 const struct ir3_shader_variant *xs,
461 if (!xs) {
467 xs->info.double_threadsize ? THREAD128 : THREAD64;
471 .fullregfootprint = xs->info.max_reg + 1,
472 .halfregfootprint = xs->info.max_half_reg + 1,
473 .branchstack = ir3_shader_branchstack_hw(xs),
474 .mergedregs = xs->mergedregs,
479 .fullregfootprint = xs->info.max_reg + 1,
480 .halfregfootprint = xs->info.max_half_reg + 1,
481 .branchstack = ir3_shader_branchstack_hw(xs),
486 .fullregfootprint = xs->info.max_reg + 1,
487 .halfregfootprint = xs->info.max_half_reg + 1,
488 .branchstack = ir3_shader_branchstack_hw(xs),
489 .mergedregs = xs->mergedregs,
494 .fullregfootprint = xs->info.max_reg + 1,
495 .halfregfootprint = xs->info.max_half_reg + 1,
496 .branchstack = ir3_shader_branchstack_hw(xs),
501 .fullregfootprint = xs->info.max_reg + 1,
502 .halfregfootprint = xs->info.max_half_reg + 1,
503 .branchstack = ir3_shader_branchstack_hw(xs),
504 .mergedregs = xs->mergedregs,
506 .pixlodenable = xs->need_pixlod,
507 .diff_fine = xs->need_fine_derivatives,
508 .varying = xs->total_in != 0,
515 .fullregfootprint = xs->info.max_reg + 1,
516 .halfregfootprint = xs->info.max_half_reg + 1,
517 .branchstack = ir3_shader_branchstack_hw(xs),
518 .mergedregs = xs->mergedregs,
527 tu_cs_emit(cs, xs->instrlen);
553 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
558 const struct ir3_const_state *const_state = ir3_const_state(xs);
560 unsigned immediate_size = tu_xs_get_immediates_packet_size_dwords(xs);
576 uint64_t iova = binary_iova + xs->info.constant_data_offset;
588 int size_vec4s = DIV_ROUND_UP(xs->constant_data_size, 16);
605 (16 * xs->constlen) - ubo_state->range[i].offset);
1661 const struct ir3_shader_variant *xs = builder->variants[stage];
1664 fs = xs = NULL;
1666 tu6_emit_xs(cs, stage, xs, &builder->pvtmem, builder->shader_iova[stage]);