Lines Matching refs:reg_mode
129 midgard_reg_mode reg_mode)
136 assert(reg_mode == midgard_reg_mode_8 ||
137 reg_mode == midgard_reg_mode_16);
141 assert(reg_mode == midgard_reg_mode_8 ||
142 reg_mode == midgard_reg_mode_16);
146 assert(reg_mode == midgard_reg_mode_8 ||
147 reg_mode == midgard_reg_mode_16);
151 assert(reg_mode != midgard_reg_mode_8);
155 assert(reg_mode != midgard_reg_mode_8);
159 assert(reg_mode == midgard_reg_mode_16);
163 assert(reg_mode == midgard_reg_mode_16);
404 midgard_reg_mode reg_mode,
436 midgard_reg_mode reg_mode,
440 assert(reg_mode != midgard_reg_mode_64);
442 unsigned mask_skip = MAX2(bits_for_mode(reg_mode) / 16, 1);
444 bool is_vec16 = reg_mode == midgard_reg_mode_8;
556 unsigned bits = bits_for_mode_halved(alu->reg_mode, expands);
633 mir_print_constant_component(fp, consts, c, alu->reg_mode,
818 midgard_reg_mode mode = alu_field->reg_mode;