Cross Reference: /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/midgard

Lines Matching refs:branch
52  * same bundle as the branch, with no hanging dependencies.
185         /* If there is a branch, all instructions depend on it, as interblock
705                 bool branch = alu && (unit == ALU_ENAB_BR_COMPACT);
713                 if (alu && !branch && unit != ~0 && !(mir_has_unit(instructions[i], unit)))
720                 if (branch && !instructions[i]->compact_branch)
741                 bool conditional = alu && !branch && OP_IS_CSEL(instructions[i]->op);
742                 conditional |= (branch && instructions[i]->branch.conditional);
861 /* When we are scheduling a branch/csel, we need the consumed condition in the
970         /* For a branch, the condition is the only argument; for csel, third */
971         bool branch = last->compact_branch;
972         unsigned condition_index = branch ? 0 : 2;
975         bool vector = !branch && OP_IS_CSEL_V(last->op);
1003          * depending on scalar/vector of the instruction itself. A branch must
1004          * be written from the latter pipeline stage and a branch condition is
1008         if (branch)
1095                 midgard_instruction *branch,
1103         unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx];
1136         branch->src[idx] = mov->dest;
1139                 unsigned swizzle = (branch->src[0] == ~0) ? COMPONENT_Y : COMPONENT_X;
1179         midgard_instruction *branch = NULL;
1181         mir_choose_alu(&branch, instructions, liveness, worklist, len, &predicate, ALU_ENAB_BR_COMPACT);
1182         mir_update_worklist(worklist, len, instructions, branch);
1183         unsigned writeout = branch ? branch->writeout : 0;
1185         if (branch && branch->branch.conditional) {
1186                 midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, branch);
1200         if (writeout && (branch->constants.u32[0] || ctx->inputs->is_blend)) {
1206                 sadd->inline_constant = branch->constants.u32[0];
1207                 branch->src[1] = sadd->dest;
1208                 branch->src_types[1] = sadd->dest_type;
1213                 bundle.last_writeout = branch->last_writeout;
1251                 branch->dest = vadd->dest;
1252                 branch->dest_type = vadd->dest_type;
1256                 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, false);
1259                 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, true);
1300                 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0];
1312                         bad_writeout |= mir_has_arg(stages[i], branch->src[0]);
1342                         unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx);
1358                         mir_rewrite_index_src_single(branch, src, temp);
1372         midgard_instruction *stages[] = { vmul, sadd, vadd, smul, vlut, branch };
1380                         /* If we branch, we can't spill to TLS since the store
1385                         if (branch)
1404         bool tilebuf_wait = branch && branch->compact_branch &&
1405            branch->branch.target_type == TARGET_TILEBUF_WAIT;