Lines Matching defs:bus

50 pci_read(int domain, int bus, int dev, int func, uint32_t reg, uint32_t *val)
56 io.pi_sel.pc_bus = bus;
72 pci_write(int domain, int bus, int dev, int func, uint32_t reg, uint32_t val)
77 io.pi_sel.pc_bus = bus;
88 pci_readmask(int domain, int bus, int dev, int func, uint32_t reg,
95 io.pi_sel.pc_bus = bus;
122 int pci_rom, domain, bus, dev, func;
128 bus = device->bus;
151 pci_read(domain, bus, dev, func, PCI_COMMAND_STATUS_REG, &csr);
152 pci_write(domain, bus, dev, func, PCI_COMMAND_STATUS_REG,
154 pci_read(domain, bus, dev, func, PCI_ROM_REG, &rom);
155 pci_write(domain, bus, dev, func, PCI_ROM_REG,
169 pci_write(domain, bus, dev, func, PCI_ROM_REG, rom);
170 pci_write(domain, bus, dev, func, PCI_COMMAND_STATUS_REG, csr);
176 pci_nfuncs(int domain, int bus, int dev)
183 if (pci_read(domain, bus, dev, 0, PCI_BHLC_REG, &hdr) != 0)
258 io.pi_sel.pc_bus = dev->bus;
295 io.pi_sel.pc_bus = dev->bus;
334 int domain, bus, dev, func, err;
337 bus = device->bus;
341 err = pci_read(domain, bus, dev, func, PCI_BHLC_REG, &reg);
352 err = pci_read(domain, bus, dev, func, bar, &reg);
357 err = pci_readmask(domain, bus, dev, func, bar, &size);
382 err = pci_read(domain, bus, dev, func, bar, &reg);
387 err = pci_readmask(domain, bus, dev, func, bar, &size);
401 err = pci_read(domain, bus, dev, func, PCI_ROM_REG, &reg);
405 err = pci_write(domain, bus, dev, func, PCI_ROM_REG, ~PCI_ROM_ENABLE);
408 pci_read(domain, bus, dev, func, PCI_ROM_REG, &size);
409 pci_write(domain, bus, dev, func, PCI_ROM_REG, reg);
587 int domain, bus, dev, func, ndevs, nfuncs;
617 for (bus = 0; bus < 256; bus++) {
619 nfuncs = pci_nfuncs(domain, bus, dev);
621 if (pci_read(domain, bus, dev, func,
647 for (bus = 0; bus < 256; bus++) {
649 nfuncs = pci_nfuncs(domain, bus, dev);
651 if (pci_read(domain, bus, dev, func,
663 device->base.bus = bus;
669 if (pci_read(domain, bus, dev, func,
679 if (pci_read(domain, bus, dev, func,
754 pv.pv_sel.pc_bus = dev->bus;
785 pv.pv_sel.pc_bus = dev->bus;
809 pv.pv_sel.pc_bus = dev->bus;