Lines Matching refs:jReg
718 UCHAR jReg;
724 jReg = pStdModePtr->MISC;
725 SetReg(MISC_PORT_WRITE,jReg);
731 jReg = pStdModePtr->SEQ[i];
732 if (!i) (jReg |= 0x20); /* display off */
733 SetIndexReg(SEQ_PORT,(UCHAR) (i+1), jReg);
740 jReg = pStdModePtr->CRTC[i];
741 SetIndexReg(CRTC_PORT,(UCHAR) i, jReg);
745 jReg = GetReg(INPUT_STATUS1_READ);
748 jReg = pStdModePtr->AR[i];
750 SetReg(AR_PORT_WRITE, jReg);
755 jReg = GetReg(INPUT_STATUS1_READ);
761 jReg = pStdModePtr->GR[i];
762 SetIndexReg(GR_PORT,(UCHAR) i, jReg);
965 UCHAR jReg;
970 jReg = GetReg(MISC_PORT_READ);
971 jReg &= ~0xC0;
972 if (pEnhModePtr->Flags & NVSync) jReg |= 0x80;
973 if (pEnhModePtr->Flags & NHSync) jReg |= 0x40;
974 SetReg(MISC_PORT_WRITE,jReg);
1291 UCHAR jReg;
1293 jReg = GetChrontelReg(pAST, 1, 0x4A); /* get vendor id */
1294 if (jReg == 0x95)
1296 jReg = GetChrontelReg(pAST, 1, 0x20); /* DVI/D-Sub */
1297 if (jReg & 0x20) /* DVI */