Lines Matching refs:accel_state
622 struct radeon_accel_state *accel_state = info->accel_state;
659 accel_state->vbo.vb_offset, 0,
664 accel_state->vbo.vb_offset, 0,
961 struct radeon_accel_state *accel_state = info->accel_state;
968 if (accel_state->XInited3D)
974 accel_state->XInited3D = TRUE;
1231 RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
1236 RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
1241 RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
1365 fs_conf.bo = accel_state->shaders_bo;
1443 struct radeon_accel_state *accel_state = info->accel_state;
1447 if (accel_state->vbo.vb_start_op == -1)
1453 if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) {
1460 accel_state->vbo.vb_size = accel_state->vbo.vb_offset - accel_state->vbo.vb_start_op;
1463 vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4;
1464 vtx_res.vb_addr = accel_state->vbo.vb_start_op;
1465 vtx_res.bo = accel_state->vbo.vb_bo;
1486 accel_state->dst_size, 0,
1487 accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
1489 accel_state->vbo.vb_start_op = -1;
1490 accel_state->cbuf.vb_start_op = -1;
1491 accel_state->ib_reset_op = 0;