Cross Reference: /xsrc/external/mit/xf86-video-ati-kms/dist/src/r600

Lines Matching refs:src_obj
59 	memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
65 	if (accel_state->src_obj[0].pitch & pitch_align)
66 	    RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch));
69 	memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
74 	memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
81 	if (accel_state->src_obj[1].pitch & pitch_align)
82 	    RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch));
85 	memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
120     if (accel_state->src_obj[0].bo)
121 	radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[0].bo,
122 					  accel_state->src_obj[0].domain, 0);
123     if (accel_state->src_obj[1].bo)
124 	radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[1].bo,
125 					  accel_state->src_obj[1].domain, 0);
375     tex_res.w                   = accel_state->src_obj[0].width;
376     tex_res.h                   = accel_state->src_obj[0].height;
377     tex_res.pitch               = accel_state->src_obj[0].pitch;
383     tex_res.bo                  = accel_state->src_obj[0].bo;
384     tex_res.mip_bo              = accel_state->src_obj[0].bo;
385     tex_res.surface             = accel_state->src_obj[0].surface;
386     if (accel_state->src_obj[0].bpp == 8) {
392     } else if (accel_state->src_obj[0].bpp == 16) {
410     if (accel_state->src_obj[0].tiling_flags == 0)
412     r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
523     struct r600_accel_object src_obj, dst_obj;
533     src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
537     src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
540     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
541     src_obj.surface = radeon_get_pixmap_surface(pSrc);
543     if (src_obj.bo == dst_obj.bo)
546     src_obj.width = pSrc->drawable.width;
547     src_obj.height = pSrc->drawable.height;
548     src_obj.bpp = pSrc->drawable.bitsPerPixel;
549     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
560 			   &src_obj,
653 	uint32_t orig_src_domain = accel_state->src_obj[0].domain;
654 	uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
669 	accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
670 	accel_state->src_obj[0].bo = accel_state->copy_area_bo;
671 	accel_state->src_obj[0].tiling_flags = 0;
681 	accel_state->src_obj[0].domain = orig_src_domain;
682 	accel_state->src_obj[0].bo = orig_bo;
683 	accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
892     tex_res.pitch               = accel_state->src_obj[unit].pitch;
899     tex_res.bo                  = accel_state->src_obj[unit].bo;
900     tex_res.mip_bo              = accel_state->src_obj[unit].bo;
901     tex_res.surface             = accel_state->src_obj[unit].surface;
905     switch (accel_state->src_obj[unit].bpp) {
1036     if (accel_state->src_obj[unit].tiling_flags == 0)
1038     r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[unit].domain);
1339     struct r600_accel_object src_obj, mask_obj, dst_obj;
1347 	src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
1348 	src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
1349 	src_obj.surface = radeon_get_pixmap_surface(pSrc);
1350 	src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
1351 	src_obj.width = pSrc->drawable.width;
1352 	src_obj.height = pSrc->drawable.height;
1353 	src_obj.bpp = pSrc->drawable.bitsPerPixel;
1354 	src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
1399 			   pSrc ? &src_obj : NULL,
1696     struct r600_accel_object src_obj, dst_obj;
1730     src_obj.pitch = scratch_pitch;
1731     src_obj.width = w;
1732     src_obj.height = h;
1733     src_obj.bpp = bpp;
1734     src_obj.domain = RADEON_GEM_DOMAIN_GTT;
1735     src_obj.bo = scratch;
1736     src_obj.tiling_flags = 0;
1737     src_obj.surface = NULL;
1749 			   &src_obj,
1815     struct r600_accel_object src_obj, dst_obj;
1856     accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
1857     radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0);
1865     src_obj.pitch = src_pitch_hw;
1866     src_obj.width = pSrc->drawable.width;
1867     src_obj.height = pSrc->drawable.height;
1868     src_obj.bpp = bpp;
1869     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
1870     src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
1871     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
1872     src_obj.surface = radeon_get_pixmap_surface(pSrc);
1884 			   &src_obj,
2083     info->accel_state->src_obj[0].bo = NULL;
2084     info->accel_state->src_obj[1].bo = NULL;