Cross Reference: /xsrc/external/mit/xf86-video-ati-kms/dist/src/radeon_bo

Lines Matching refs:surface
111 radeon_surface_initialize(RADEONInfoPtr info, struct radeon_surface *surface,
115 	memset(surface, 0, sizeof(struct radeon_surface));
117 	surface->npix_x = width;
119 	surface->npix_y = RADEON_ALIGN(height, 8);
120 	surface->npix_z = 1;
121 	surface->blk_w = 1;
122 	surface->blk_h = 1;
123 	surface->blk_d = 1;
124 	surface->array_size = 1;
125 	surface->last_level = 0;
126 	surface->bpe = cpp;
127 	surface->nsamples = 1;
129 	    /* disable 2d tiling for small surface to work around
136 	surface->flags = RADEON_SURF_SCANOUT | RADEON_SURF_HAS_TILE_MODE_INDEX |
140 	    surface->flags |= RADEON_SURF_ZBUFFER;
141 	    surface->flags |= RADEON_SURF_SBUFFER;
145 	    surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
146 	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
148 	    surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
149 	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
151 	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
154 	    surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
156 	    surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) &
158 	    surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) &
160 	    if (surface->flags & RADEON_SURF_SBUFFER) {
161 		surface->stencil_tile_split =
165 	    surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
169 	if (radeon_surface_best(info->surf_man, surface))
172 	if (radeon_surface_init(info->surf_man, surface))
191     struct radeon_surface surface;
270 	if (!radeon_surface_initialize(info, &surface, width, height, cpp,
274 	size = surface.bo_size;
275 	base_align = surface.bo_alignment;
276 	pitch = surface.level[0].pitch_bytes;
278 	switch (surface.level[0].mode) {
281 	    tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
282 	    tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
283 	    tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
284 	    if (surface.tile_split)
285 		tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
286 	    if (surface.flags & RADEON_SURF_SBUFFER)
287 		tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
297 	    *new_surface = surface;
452 				      struct radeon_surface *surface)
515     if (surface) {
522 	if (!radeon_surface_initialize(info, surface, ppix->drawable.width,
530 	/* we have to post hack the surface to reflect the actual size
532 	surface->level[0].pitch_bytes = ppix->devKind;
533 	surface->level[0].nblk_x = ppix->devKind / surface->bpe;