Lines Matching refs:lane
585 5400, // 1 lane, 1.62 Ghz
586 9000, // 1 lane, 2.70 Ghz
587 10800, // 2 lane, 1.62 Ghz
588 18000, // 2 lane, 2.70 Ghz
589 21600, // 4 lane, 1.62 Ghz
590 36000, // 4 lane, 2.70 Ghz
2414 static uint8_t dp_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane)
2416 int i = DP_LANE0_1_STATUS + (lane >> 1);
2417 int s = (lane & 1) * 4;
2424 int lane;
2428 for (lane = 0; lane < lane_count; lane++) {
2429 lane_status = dp_get_lane_status(link_status, lane);
2446 int lane;
2452 for (lane = 0; lane < lane_count; lane++) {
2453 lane_status = dp_get_lane_status(link_status, lane);
2484 int lane)
2487 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
2488 int s = ((lane & 1) ?
2498 int lane)
2500 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
2501 int s = ((lane & 1) ?
2561 int lane;
2563 for (lane = 0; lane < lane_count; lane++) {
2564 uint8_t this_v = dp_get_adjust_request_voltage(link_status, lane);
2565 uint8_t this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
2569 "requested signal parameters: lane %d voltage %s pre_emph %s\n",
2570 lane,
2592 for (lane = 0; lane < 4; lane++)
2593 train_set[lane] = v | p;