Lines Matching refs:accel_state
63 struct radeon_accel_state *accel_state = info->accel_state;
92 accel_state->solid_vs_offset, accel_state->solid_ps_offset,
101 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
102 radeon_vbo_check(pScrn, &accel_state->cbuf, 256);
107 evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
108 evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
109 evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
112 vs_conf.shader_addr = accel_state->vs_mc_addr;
113 vs_conf.shader_size = accel_state->vs_size;
116 vs_conf.bo = accel_state->shaders_bo;
119 ps_conf.shader_addr = accel_state->ps_mc_addr;
120 ps_conf.shader_size = accel_state->ps_size;
125 ps_conf.bo = accel_state->shaders_bo;
129 cb_conf.w = accel_state->dst_obj.pitch;
130 cb_conf.h = accel_state->dst_obj.height;
131 cb_conf.base = accel_state->dst_obj.offset;
132 cb_conf.bo = accel_state->dst_obj.bo;
133 cb_conf.surface = accel_state->dst_obj.surface;
135 if (accel_state->dst_obj.bpp == 8) {
138 } else if (accel_state->dst_obj.bpp == 16) {
154 if (accel_state->planemask & 0x000000ff)
156 if (accel_state->planemask & 0x0000ff00)
158 if (accel_state->planemask & 0x00ff0000)
160 if (accel_state->planemask & 0xff000000)
162 cb_conf.rop = accel_state->rop;
163 if (accel_state->dst_obj.tiling_flags == 0) {
167 evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
174 ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
175 ps_const_conf.bo = accel_state->cbuf.vb_bo;
176 ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset;
178 if (accel_state->dst_obj.bpp == 16) {
186 } else if (accel_state->dst_obj.bpp == 8) {
202 radeon_vbo_commit(pScrn, &accel_state->cbuf);
205 if (accel_state->vsync)
208 accel_state->dst_pix = pPix;
209 accel_state->fg = fg;
219 struct radeon_accel_state *accel_state = info->accel_state;
221 if (accel_state->vsync)
223 accel_state->vline_crtc,
224 accel_state->vline_y1,
225 accel_state->vline_y2);
235 struct radeon_accel_state *accel_state = info->accel_state;
239 EVERGREENDoneSolid(info->accel_state->dst_pix);
241 EVERGREENPrepareSolid(accel_state->dst_pix,
242 accel_state->rop,
243 accel_state->planemask,
244 accel_state->fg);
247 if (accel_state->vsync)
250 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 8);
261 radeon_vbo_commit(pScrn, &accel_state->vbo);
268 struct radeon_accel_state *accel_state = info->accel_state;
280 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
285 evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
286 evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
287 evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
290 vs_conf.shader_addr = accel_state->vs_mc_addr;
291 vs_conf.shader_size = accel_state->vs_size;
294 vs_conf.bo = accel_state->shaders_bo;
297 ps_conf.shader_addr = accel_state->ps_mc_addr;
298 ps_conf.shader_size = accel_state->ps_size;
303 ps_conf.bo = accel_state->shaders_bo;
308 tex_res.w = accel_state->src_obj[0].width;
309 tex_res.h = accel_state->src_obj[0].height;
310 tex_res.pitch = accel_state->src_obj[0].pitch;
313 tex_res.base = accel_state->src_obj[0].offset;
314 tex_res.mip_base = accel_state->src_obj[0].offset;
315 tex_res.size = accel_state->src_size[0];
316 tex_res.bo = accel_state->src_obj[0].bo;
317 tex_res.mip_bo = accel_state->src_obj[0].bo;
318 tex_res.surface = accel_state->src_obj[0].surface;
319 if (accel_state->src_obj[0].bpp == 8) {
325 } else if (accel_state->src_obj[0].bpp == 16) {
342 if (accel_state->src_obj[0].tiling_flags == 0)
344 evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
358 cb_conf.w = accel_state->dst_obj.pitch;
359 cb_conf.h = accel_state->dst_obj.height;
360 cb_conf.base = accel_state->dst_obj.offset;
361 cb_conf.bo = accel_state->dst_obj.bo;
362 cb_conf.surface = accel_state->dst_obj.surface;
363 if (accel_state->dst_obj.bpp == 8) {
366 } else if (accel_state->dst_obj.bpp == 16) {
376 if (accel_state->planemask & 0x000000ff)
378 if (accel_state->planemask & 0x0000ff00)
380 if (accel_state->planemask & 0x00ff0000)
382 if (accel_state->planemask & 0xff000000)
384 cb_conf.rop = accel_state->rop;
385 if (accel_state->dst_obj.tiling_flags == 0) {
389 evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
406 struct radeon_accel_state *accel_state = info->accel_state;
408 if (accel_state->vsync)
410 accel_state->vline_crtc,
411 accel_state->vline_y1,
412 accel_state->vline_y2);
424 struct radeon_accel_state *accel_state = info->accel_state;
427 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
444 radeon_vbo_commit(pScrn, &accel_state->vbo);
455 struct radeon_accel_state *accel_state = info->accel_state;
468 accel_state->same_surface = FALSE;
479 accel_state->same_surface = TRUE;
495 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
499 if (accel_state->same_surface == TRUE) {
501 drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
502 unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
504 if (accel_state->dst_obj.surface)
505 size = accel_state->dst_obj.surface->bo_size;
507 if (accel_state->copy_area_bo) {
508 radeon_bo_unref(accel_state->copy_area_bo);
509 accel_state->copy_area_bo = NULL;
511 accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
514 if (accel_state->copy_area_bo == NULL)
517 radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
520 radeon_bo_unref(accel_state->copy_area_bo);
521 accel_state->copy_area_bo = NULL;
524 accel_state->copy_area = (void*)accel_state->copy_area_bo;
528 if (accel_state->vsync)
531 accel_state->dst_pix = pDst;
532 accel_state->src_pix = pSrc;
533 accel_state->xdir = xdir;
534 accel_state->ydir = ydir;
544 struct radeon_accel_state *accel_state = info->accel_state;
546 if (!accel_state->same_surface)
549 if (accel_state->copy_area)
550 accel_state->copy_area = NULL;
562 struct radeon_accel_state *accel_state = info->accel_state;
564 if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY))
568 EVERGREENDoneCopy(info->accel_state->dst_pix);
570 EVERGREENPrepareCopy(accel_state->src_pix,
571 accel_state->dst_pix,
572 accel_state->xdir,
573 accel_state->ydir,
574 accel_state->rop,
575 accel_state->planemask);
578 if (accel_state->vsync)
581 if (accel_state->same_surface && accel_state->copy_area) {
582 uint32_t orig_dst_domain = accel_state->dst_obj.domain;
583 uint32_t orig_src_domain = accel_state->src_obj[0].domain;
584 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
585 uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
586 struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
587 int orig_rop = accel_state->rop;
588 struct radeon_surface *orig_dst_surface = accel_state->dst_obj.surface;
589 struct radeon_surface *orig_src_surface = accel_state->src_obj[0].surface;
592 accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
593 accel_state->dst_obj.bo = accel_state->copy_area_bo;
594 accel_state->dst_obj.offset = 0;
595 accel_state->dst_obj.tiling_flags = 0;
596 accel_state->rop = 3;
597 accel_state->dst_obj.surface = NULL;
603 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
604 accel_state->src_obj[0].bo = accel_state->copy_area_bo;
605 accel_state->src_obj[0].offset = 0;
606 accel_state->src_obj[0].tiling_flags = 0;
607 accel_state->src_obj[0].surface = NULL;
608 accel_state->dst_obj.domain = orig_dst_domain;
609 accel_state->dst_obj.bo = orig_bo;
610 accel_state->dst_obj.offset = 0;
611 accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
612 accel_state->rop = orig_rop;
613 accel_state->dst_obj.surface = orig_dst_surface;
619 accel_state->src_obj[0].domain = orig_src_domain;
620 accel_state->src_obj[0].bo = orig_bo;
621 accel_state->src_obj[0].offset = 0;
622 accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
623 accel_state->src_obj[0].surface = orig_src_surface;
791 struct radeon_accel_state *accel_state = info->accel_state;
804 accel_state->is_transform[unit] = TRUE;
805 accel_state->transform[unit] = pPict->transform;
817 accel_state->is_transform[unit] = FALSE;
837 struct radeon_accel_state *accel_state = info->accel_state;
864 tex_res.pitch = accel_state->src_obj[unit].pitch;
867 tex_res.base = accel_state->src_obj[unit].offset;
868 tex_res.mip_base = accel_state->src_obj[unit].offset;
869 tex_res.size = accel_state->src_size[unit];
871 tex_res.bo = accel_state->src_obj[unit].bo;
872 tex_res.mip_bo = accel_state->src_obj[unit].bo;
873 tex_res.surface = accel_state->src_obj[unit].surface;
876 switch (accel_state->src_obj[unit].bpp) {
942 if (!accel_state->msk_pic) {
952 if (accel_state->component_alpha) {
953 if (accel_state->src_alpha) {
980 if (accel_state->component_alpha) {
1005 if (accel_state->src_obj[unit].tiling_flags == 0)
1007 evergreen_set_tex_resource (pScrn, &tex_res, accel_state->src_obj[unit].domain);
1136 struct radeon_accel_state *accel_state = info->accel_state;
1197 accel_state->comp_vs_offset, accel_state->comp_ps_offset,
1201 accel_state->msk_pic = pMaskPicture;
1203 accel_state->component_alpha = TRUE;
1205 accel_state->src_alpha = TRUE;
1207 accel_state->src_alpha = FALSE;
1209 accel_state->component_alpha = FALSE;
1210 accel_state->src_alpha = FALSE;
1217 accel_state->comp_vs_offset, accel_state->comp_ps_offset,
1221 accel_state->msk_pic = NULL;
1222 accel_state->component_alpha = FALSE;
1223 accel_state->src_alpha = FALSE;
1235 radeon_vbo_check(pScrn, &accel_state->vbo, 24);
1237 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
1239 radeon_vbo_check(pScrn, &accel_state->cbuf, 256);
1245 evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1246 evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1247 evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1262 accel_state->is_transform[1] = FALSE;
1273 vs_conf.shader_addr = accel_state->vs_mc_addr;
1274 vs_conf.shader_size = accel_state->vs_size;
1277 vs_conf.bo = accel_state->shaders_bo;
1280 ps_conf.shader_addr = accel_state->ps_mc_addr;
1281 ps_conf.shader_size = accel_state->ps_size;
1286 ps_conf.bo = accel_state->shaders_bo;
1290 cb_conf.w = accel_state->dst_obj.pitch;
1291 cb_conf.h = accel_state->dst_obj.height;
1292 cb_conf.base = accel_state->dst_obj.offset;
1294 cb_conf.bo = accel_state->dst_obj.bo;
1295 cb_conf.surface = accel_state->dst_obj.surface;
1328 if (accel_state->dst_obj.tiling_flags == 0) {
1344 evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
1354 cbuf = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
1355 vs_const_conf.bo = accel_state->cbuf.vb_bo;
1356 vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset;
1363 radeon_vbo_commit(pScrn, &accel_state->cbuf);
1366 if (accel_state->vsync)
1369 accel_state->composite_op = op;
1370 accel_state->dst_pic = pDstPicture;
1371 accel_state->src_pic = pSrcPicture;
1372 accel_state->dst_pix = pDst;
1373 accel_state->msk_pix = pMask;
1374 accel_state->src_pix = pSrc;
1380 struct radeon_accel_state *accel_state)
1384 if (accel_state->vsync)
1386 accel_state->vline_crtc,
1387 accel_state->vline_y1,
1388 accel_state->vline_y2);
1390 vtx_size = accel_state->msk_pic ? 24 : 16;
1400 struct radeon_accel_state *accel_state = info->accel_state;
1402 EVERGREENFinishComposite(pScrn, pDst, accel_state);
1404 if (!accel_state->src_pic->pDrawable)
1405 pScreen->DestroyPixmap(accel_state->src_pix);
1407 if (accel_state->msk_pic && !accel_state->msk_pic->pDrawable)
1408 pScreen->DestroyPixmap(accel_state->msk_pix);
1419 struct radeon_accel_state *accel_state = info->accel_state;
1423 EVERGREENFinishComposite(pScrn, pDst, info->accel_state);
1425 EVERGREENPrepareComposite(info->accel_state->composite_op,
1426 info->accel_state->src_pic,
1427 info->accel_state->msk_pic,
1428 info->accel_state->dst_pic,
1429 info->accel_state->src_pix,
1430 info->accel_state->msk_pix,
1431 info->accel_state->dst_pix);
1434 if (accel_state->vsync)
1437 if (accel_state->msk_pic) {
1439 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 24);
1462 radeon_vbo_commit(pScrn, &accel_state->vbo);
1466 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
1483 radeon_vbo_commit(pScrn, &accel_state->vbo);
1495 struct radeon_accel_state *accel_state = info->accel_state;
1564 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1593 if (info->accel_state->vsync)
1614 struct radeon_accel_state *accel_state = info->accel_state;
1658 if (!accel_state->allowHWDFS)
1670 radeon_cs_space_add_persistent_bo(info->cs, info->accel_state->shaders_bo,
1672 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
1673 radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0);
1674 accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
1675 radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain);
1705 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1751 struct radeon_accel_state *accel_state = info->accel_state;
1753 return ++accel_state->exaSyncMarker;
1767 struct radeon_accel_state *accel_state = info->accel_state;
1772 accel_state->shaders = NULL;
1774 accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
1776 if (accel_state->shaders_bo == NULL) {
1787 struct radeon_accel_state *accel_state = info->accel_state;
1792 ret = radeon_bo_map(accel_state->shaders_bo, 1);
1797 shader = accel_state->shaders_bo->ptr;
1800 accel_state->solid_vs_offset = 0;
1801 evergreen_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4);
1804 accel_state->solid_ps_offset = 512;
1805 evergreen_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4);
1808 accel_state->copy_vs_offset = 1024;
1809 evergreen_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4);
1812 accel_state->copy_ps_offset = 1536;
1813 evergreen_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4);
1816 accel_state->comp_vs_offset = 2048;
1817 evergreen_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4);
1820 accel_state->comp_ps_offset = 2560;
1821 evergreen_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4);
1824 accel_state->xv_vs_offset = 3072;
1825 evergreen_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4);
1828 accel_state->xv_ps_offset = 3584;
1829 evergreen_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
1831 radeon_bo_unmap(accel_state->shaders_bo);
1840 struct radeon_accel_state *accel_state = info->accel_state;
1845 ret = radeon_bo_map(accel_state->shaders_bo, 1);
1850 shader = accel_state->shaders_bo->ptr;
1853 accel_state->solid_vs_offset = 0;
1854 cayman_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4);
1857 accel_state->solid_ps_offset = 512;
1858 cayman_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4);
1861 accel_state->copy_vs_offset = 1024;
1862 cayman_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4);
1865 accel_state->copy_ps_offset = 1536;
1866 cayman_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4);
1869 accel_state->comp_vs_offset = 2048;
1870 cayman_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4);
1873 accel_state->comp_ps_offset = 2560;
1874 cayman_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4);
1877 accel_state->xv_vs_offset = 3072;
1878 cayman_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4);
1881 accel_state->xv_ps_offset = 3584;
1882 cayman_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
1884 radeon_bo_unmap(accel_state->shaders_bo);
1895 if (info->accel_state->exa == NULL) {
1904 info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
1905 info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
1907 info->accel_state->exa->PrepareSolid = EVERGREENPrepareSolid;
1908 info->accel_state->exa->Solid = EVERGREENSolid;
1909 info->accel_state->exa->DoneSolid = EVERGREENDoneSolid;
1911 info->accel_state->exa->PrepareCopy = EVERGREENPrepareCopy;
1912 info->accel_state->exa->Copy = EVERGREENCopy;
1913 info->accel_state->exa->DoneCopy = EVERGREENDoneCopy;
1915 info->accel_state->exa->MarkSync = EVERGREENMarkSync;
1916 info->accel_state->exa->WaitMarker = EVERGREENSync;
1918 info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
1919 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
1920 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
1921 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
1922 info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
1923 info->accel_state->exa->UploadToScreen = EVERGREENUploadToScreen;
1924 info->accel_state->exa->DownloadFromScreen = EVERGREENDownloadFromScreen;
1926 info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
1929 info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS;
1931 info->accel_state->exa->flags |= EXA_SUPPORTS_PREPARE_AUX;
1935 info->accel_state->exa->flags |= EXA_HANDLES_PIXMAPS;
1937 info->accel_state->exa->flags |= EXA_MIXED_PIXMAPS;
1940 info->accel_state->exa->pixmapOffsetAlign = 256;
1941 info->accel_state->exa->pixmapPitchAlign = 256;
1943 info->accel_state->exa->CheckComposite = EVERGREENCheckComposite;
1944 info->accel_state->exa->PrepareComposite = EVERGREENPrepareComposite;
1945 info->accel_state->exa->Composite = EVERGREENComposite;
1946 info->accel_state->exa->DoneComposite = EVERGREENDoneComposite;
1951 info->accel_state->exa->maxPitchBytes = 32768;
1952 info->accel_state->exa->maxX = 8192;
1954 info->accel_state->exa->maxX = 8192;
1956 info->accel_state->exa->maxY = 8192;
1961 info->accel_state->vsync = TRUE;
1963 info->accel_state->vsync = FALSE;
1965 if (!exaDriverInit(pScreen, info->accel_state->exa)) {
1966 free(info->accel_state->exa);
1970 info->accel_state->XInited3D = FALSE;
1971 info->accel_state->copy_area = NULL;
1972 info->accel_state->src_obj[0].bo = NULL;
1973 info->accel_state->src_obj[1].bo = NULL;
1974 info->accel_state->dst_obj.bo = NULL;
1975 info->accel_state->copy_area_bo = NULL;
1976 info->accel_state->vbo.vb_start_op = -1;
1977 info->accel_state->cbuf.vb_start_op = -1;
1978 info->accel_state->finish_op = evergreen_finish_op;
1979 info->accel_state->vbo.verts_per_op = 3;
1980 info->accel_state->cbuf.verts_per_op = 1;