Lines Matching refs:INREG
101 tmp = INREG(RADEON_DAC_CNTL2);
504 save->ovr_clr = INREG(RADEON_OVR_CLR);
505 save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT);
506 save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM);
507 save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
508 save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL);
509 save->viph_control = INREG(RADEON_VIPH_CONTROL);
510 save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1);
511 save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
512 save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL);
513 save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL);
514 save->bus_cntl = INREG(RADEON_BUS_CNTL);
515 save->surface_cntl = INREG(RADEON_SURFACE_CNTL);
516 save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL);
517 save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL);
521 save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1);
522 save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2);
523 save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1);
524 save->disp1_req_cntl1 = INREG(RS400_DISP1_REQ_CNTL1);
535 save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
536 save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
537 save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP);
538 save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID);
539 save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP);
540 save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID);
542 save->crtc_offset = INREG(RADEON_CRTC_OFFSET);
543 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
544 save->crtc_pitch = INREG(RADEON_CRTC_PITCH);
545 save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL);
548 save->crtc_tile_x0_y0 = INREG(R300_CRTC_TILE_X0_Y0);
551 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
552 save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
553 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG);
554 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
572 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
573 save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP);
574 save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID);
575 save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP);
576 save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID);
578 save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET);
579 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
580 save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH);
583 save->crtc2_tile_x0_y0 = INREG(R300_CRTC2_TILE_X0_Y0);
585 save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID);
586 save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID);
588 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL);
661 info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
816 /*save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;*/
1038 /*save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;*/
1405 uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
1439 temp = INREG(RADEON_MEM_TIMING_CNTL);
1474 temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
1495 temp = INREG(RADEON_MEM_CNTL);
1499 temp = INREG(R300_MC_IND_INDEX);
1503 temp = INREG(R300_MC_IND_DATA);
1506 temp = INREG(R300_MC_READ_CNTL_AB);
1510 temp = INREG(R300_MC_READ_CNTL_AB);
1677 (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
1759 (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL));