Lines Matching defs:dst_obj
69 struct r600_accel_object src_obj, dst_obj;
169 dst_obj.offset = 0;
171 dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
172 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
173 dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
177 dst_obj.offset = exaGetPixmapOffset(pPixmap) + info->fbLocation + pScrn->fbOffset;
179 dst_obj.bo = src_obj.bo = NULL;
181 dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8);
194 dst_obj.width = pPixmap->drawable.width;
195 dst_obj.height = pPixmap->drawable.height;
196 dst_obj.bpp = pPixmap->drawable.bitsPerPixel;
197 dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
202 &dst_obj,
220 r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
221 r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
222 r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
411 cb_conf.w = accel_state->dst_obj.pitch;
412 cb_conf.h = accel_state->dst_obj.height;
413 cb_conf.base = accel_state->dst_obj.offset;
414 cb_conf.bo = accel_state->dst_obj.bo;
417 cb_conf.surface = accel_state->dst_obj.surface;
420 switch (accel_state->dst_obj.bpp) {
448 if (accel_state->dst_obj.tiling_flags == 0)
450 r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);