Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/radeon

Lines Matching refs:OUTREG
62        OUTREG(RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK);
84        OUTREG(VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);
122    OUTREG(RADEON_VIPH_REG_ADDR, address | 0x2000);
134    OUTREG(RADEON_VIPH_TIMEOUT_STAT, INREG(RADEON_VIPH_TIMEOUT_STAT) & (0xffffff00 & ~RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
150     OUTREG(RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);         
169      OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
188    OUTREG(VIPH_REG_ADDR, address | 0x3000);
201    OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
219     OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);         
240      OUTREG(VIPH_TIMEOUT_STAT, (INREG(VIPH_TIMEOUT_STAT) & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
264     OUTREG(RADEON_VIPH_REG_ADDR, address & (~0x2000));
272              OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer);
291     OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000);
303 		OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i));
329 	    OUTREG(RADEON_VIPH_CONTROL, 0x003F0009); /* slowest, timeout in 16 phases */
330 	    OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
331 	    OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
332 	    OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
333 	    OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
336 	    OUTREG(RADEON_VIPH_CONTROL, 0x003F000D); /* slowest, timeout in 16 phases */
337 	    OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
338 	    OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
339 	    OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
340 	    OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
343 	    OUTREG(RADEON_VIPH_CONTROL, 0x003F0004); /* slowest, timeout in 16 phases */
344 	    OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
345 	    OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
346 	    OUTREG(RADEON_VIPH_BM_CHUNK, 0x151);
347 	    OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));