Lines Matching refs:RT_regw
28 #define RT_regw(reg,data) theatre_write(t,(reg),(data))
607 if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE)
1885 RT_regw (VIP_PLL_CNTL1, data & ~((RT_VINRST_RESET << 1) | (RT_L54RST_RESET << 3)));
1890 RT_regw (VIP_CLOCK_SEL_CNTL, data | (RT_PLL_VIN_CLK << 7));
1895 RT_regw (VIP_HW_DEBUG, 0x0000F000);
1905 RT_regw (VIP_DVS_PORT_CTRL, data | RT_DVSDIR_OUT);
1910 RT_regw (VIP_ADC_CNTL, RT_ADC_CNTL_DEFAULT);
1915 RT_regw (VIP_MASTER_CNTL, data & ~0x20);
1920 RT_regw (VIP_MASTER_CNTL, data & ~(RT_DVS_ASYNC_RST));
1924 RT_regw (VIP_HS_GENLOCKDELAY, 0x10);
1927 RT_regw (fld_DVS_DIRECTION, data & RT_DVSDIR_OUT);
2166 RT_regw(VIP_CLKOUT_CNTL, 0x0);
2167 RT_regw(VIP_HCOUNT, 0x0);
2168 RT_regw(VIP_VCOUNT, 0x0);
2169 RT_regw(VIP_DFCOUNT, 0x0);
2171 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */
2172 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039);
2174 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0);
2180 /* RT_regw(VIP_HW_DEBUG, 0x200); */
2181 /* RT_regw(VIP_INT_CNTL, 0x0);
2182 RT_regw(VIP_GPIO_INOUT, 0x10090000);
2183 RT_regw(VIP_GPIO_INOUT, 0x340b0000); */
2184 /* RT_regw(VIP_MASTER_CNTL, 0x6e8); */
2185 RT_regw(VIP_CLKOUT_CNTL, 0x29);
2187 RT_regw(VIP_HCOUNT, 0x1d1);
2188 RT_regw(VIP_VCOUNT, 0x1e3);
2190 RT_regw(VIP_HCOUNT, 0x322);
2191 RT_regw(VIP_VCOUNT, 0x151);
2193 RT_regw(VIP_DFCOUNT, 0x01);
2194 /* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */
2195 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */
2196 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039);
2197 /* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */
2198 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f);
2199 /* RT_regw(VIP_ADC_CNTL, 0x02a420a8);
2200 RT_regw(VIP_COMB_CNTL_0, 0x0d438083);
2201 RT_regw(VIP_COMB_CNTL_2, 0x06080102);
2202 RT_regw(VIP_HS_MINMAXWIDTH, 0x462f);
2206 RT_regw(VIP_HS_PULSE_WIDTH, 0x359);
2207 RT_regw(VIP_HS_PLL_ERROR, 0xab6);
2208 RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8);
2209 RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005);