Cross Reference: /xsrc/external/mit/xf86-video-chips/dist/src/ct

Lines Matching defs:vclk
169 				 unsigned char *vclk);
2178 		unsigned char vclk[3];
2181 		chipsCalcClock(pScrn, MemClk->Clk, vclk);
2182 		MemClk->M = vclk[1] + 2;
2183 		MemClk->N = vclk[2] + 2;
2184 		MemClk->P = (vclk[0] & 0x70) >> 4;
2185 		MemClk->PSN = (vclk[0] & 0x1) ? 1 : 4;
2186 		MemClk->xrCC = vclk[1];
2187 		MemClk->xrCD = vclk[2];
2188 		MemClk->xrCE = 0x80 || vclk[0];
4875     unsigned char vclk[3];       
4915 	    chipsCalcClock(pScrn, Clock->Clock, vclk);
4917 	    cPtr->writeXR(cPtr, 0xC0 + tmp, (vclk[1] & 0xFF));
4918 	    cPtr->writeXR(cPtr, 0xC1 + tmp, (vclk[2] & 0xFF));
4920 	    cPtr->writeXR(cPtr, 0xC3 + tmp, (vclk[0] & 0xFF));
4923     	        chipsCalcClock(pScrn, Clock->FPClock, vclk);
4925 		cPtr->writeXR(cPtr, 0xC0 + tmp, (vclk[1] & 0xFF));
4926 		cPtr->writeXR(cPtr, 0xC1 + tmp, (vclk[2] & 0xFF));
4928 		cPtr->writeXR(cPtr, 0xC3 + tmp, (vclk[0] & 0xFF));
4949 	    chipsCalcClock(pScrn, Clock->Clock, vclk);
4952 	    cPtr->writeXR(cPtr, 0x30, vclk[0]);
4953 	    cPtr->writeXR(cPtr, 0x31, vclk[1]);     /* restore VCLK regs.   */
4954 	    cPtr->writeXR(cPtr, 0x32, vclk[2]);
4978 		chipsCalcClock(pScrn, cPtr->MemClock.Clk, vclk);
4981 		cPtr->writeXR(cPtr, 0x30, vclk[0]);
4982 		cPtr->writeXR(cPtr, 0x31, vclk[1]);
4983 		cPtr->writeXR(cPtr, 0x32, vclk[2]);
4986 	    chipsCalcClock(pScrn, Clock->Clock, vclk);
4988 	    cPtr->writeXR(cPtr, 0x30, vclk[0]);
4989 	    cPtr->writeXR(cPtr, 0x31, vclk[1]);     /* restore VCLK regs.   */
4990 	    cPtr->writeXR(cPtr, 0x32, vclk[2]);
5011 chipsCalcClock(ScrnInfoPtr pScrn, int Clock, unsigned char *vclk)
5141     vclk[0] = (bestP << (IS_HiQV(cPtr) ? 4 : 1)) +
5144     vclk[1] = bestM - 2;
5145     vclk[2] = bestN - 2;
5147     ErrorF("Freq. selected: %.2f MHz, vclk[0]=%X, vclk[1]=%X, vclk[2]=%X\n",
5148 	(float)(Clock / 1000.), vclk[0], vclk[1], vclk[2]);