Cross Reference: /xsrc/external/mit/xf86-video-geode/dist/src/cim/cim

Lines Matching refs:WRITE_REG32
253     WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
257     WRITE_REG32(DC3_GENERAL_CFG, gcfg);
258     WRITE_REG32(DC3_LINE_SIZE, vg_line);
259     WRITE_REG32(DC3_VID_YUV_PITCH, pitch);
265         WRITE_REG32(DC3_VID_EVEN_Y_ST_OFFSET, video_source_even->y_offset);
266         WRITE_REG32(DC3_VID_EVEN_U_ST_OFFSET, video_source_even->u_offset);
267         WRITE_REG32(DC3_VID_EVEN_V_ST_OFFSET, video_source_even->v_offset);
270     WRITE_REG32(DC3_VID_Y_ST_OFFSET, video_source_odd->y_offset);
271     WRITE_REG32(DC3_VID_U_ST_OFFSET, video_source_odd->u_offset);
272     WRITE_REG32(DC3_VID_V_ST_OFFSET, video_source_odd->v_offset);
274     WRITE_REG32(DC3_UNLOCK, lock);
293     WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
296         WRITE_REG32(DC3_VID_EVEN_Y_ST_OFFSET, y_offset);
297         WRITE_REG32(DC3_VID_EVEN_U_ST_OFFSET, u_offset);
298         WRITE_REG32(DC3_VID_EVEN_V_ST_OFFSET, v_offset);
301         WRITE_REG32(DC3_VID_Y_ST_OFFSET, y_offset);
302         WRITE_REG32(DC3_VID_U_ST_OFFSET, u_offset);
303         WRITE_REG32(DC3_VID_V_ST_OFFSET, v_offset);
306     WRITE_REG32(DC3_UNLOCK, lock);
410         WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
419             WRITE_REG32(DC3_VID_DS_DELTA, downscale);
425         WRITE_REG32(DC3_GENERAL_CFG, gcfg);
426         WRITE_REG32(DC3_UNLOCK, unlock);
719     WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
720     WRITE_REG32(DC3_CLR_KEY_X, ckey_x);
721     WRITE_REG32(DC3_CLR_KEY_Y, ckey_y);
726     WRITE_REG32(DC3_UNLOCK, unlock);
833     WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
834     WRITE_REG32(DC3_DISPLAY_CFG, dcfg | (fifo << 16));
841         WRITE_REG32(DC3_GENERAL_CFG, (gcfg | DC3_GCFG_VIDE));
855             WRITE_REG32(DC3_COLOR_KEY, (vg_ckey & ~DC3_CLR_KEY_ENABLE));
861             WRITE_REG32(DC3_COLOR_KEY, (vg_ckey | DC3_CLR_KEY_ENABLE));
866         WRITE_REG32(DC3_GENERAL_CFG, (gcfg & ~DC3_GCFG_VIDE));
875         WRITE_REG32(DC3_COLOR_KEY, (vg_ckey & ~DC3_CLR_KEY_ENABLE));
877     WRITE_REG32(DC3_UNLOCK, lock);
897     WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
912         WRITE_REG32(DC3_COLOR_KEY, vg_ckey);
913         WRITE_REG32(DC3_COLOR_MASK, (mask & 0xFFFFFF));
921         WRITE_REG32(DC3_COLOR_KEY, vg_ckey);
927     WRITE_REG32(DC3_UNLOCK, lock);