Lines Matching defs:vg_state
2585 vg_save_state(VG_SAVE_RESTORE * vg_state)
2594 vg_state->unlock = READ_REG32(DC3_UNLOCK);
2595 vg_state->gcfg = READ_REG32(DC3_GENERAL_CFG);
2596 vg_state->dcfg = READ_REG32(DC3_DISPLAY_CFG);
2597 vg_state->arb_cfg = READ_REG32(DC3_ARB_CFG);
2598 vg_state->fb_offset = READ_REG32(DC3_FB_ST_OFFSET);
2599 vg_state->cb_offset = READ_REG32(DC3_CB_ST_OFFSET);
2600 vg_state->cursor_offset = READ_REG32(DC3_CURS_ST_OFFSET);
2601 vg_state->video_y_offset = READ_REG32(DC3_VID_Y_ST_OFFSET);
2602 vg_state->video_u_offset = READ_REG32(DC3_VID_U_ST_OFFSET);
2603 vg_state->video_v_offset = READ_REG32(DC3_VID_V_ST_OFFSET);
2604 vg_state->dv_top = READ_REG32(DC3_DV_TOP);
2605 vg_state->line_size = READ_REG32(DC3_LINE_SIZE);
2606 vg_state->gfx_pitch = READ_REG32(DC3_GFX_PITCH);
2607 vg_state->video_yuv_pitch = READ_REG32(DC3_VID_YUV_PITCH);
2608 vg_state->h_active = READ_REG32(DC3_H_ACTIVE_TIMING);
2609 vg_state->h_blank = READ_REG32(DC3_H_BLANK_TIMING);
2610 vg_state->h_sync = READ_REG32(DC3_H_SYNC_TIMING);
2611 vg_state->v_active = READ_REG32(DC3_V_ACTIVE_TIMING);
2612 vg_state->v_blank = READ_REG32(DC3_V_BLANK_TIMING);
2613 vg_state->v_sync = READ_REG32(DC3_V_SYNC_TIMING);
2614 vg_state->fb_active = READ_REG32(DC3_FB_ACTIVE);
2615 vg_state->cursor_x = READ_REG32(DC3_CURSOR_X);
2616 vg_state->cursor_y = READ_REG32(DC3_CURSOR_Y);
2617 vg_state->vid_ds_delta = READ_REG32(DC3_VID_DS_DELTA);
2618 vg_state->fb_base = READ_REG32(DC3_PHY_MEM_OFFSET);
2619 vg_state->dv_ctl = READ_REG32(DC3_DV_CTL);
2620 vg_state->gfx_scale = READ_REG32(DC3_GFX_SCALE);
2621 vg_state->irq_ctl = READ_REG32(DC3_IRQ_FILT_CTL);
2622 vg_state->vbi_even_ctl = READ_REG32(DC3_VBI_EVEN_CTL);
2623 vg_state->vbi_odd_ctl = READ_REG32(DC3_VBI_ODD_CTL);
2624 vg_state->vbi_hor_ctl = READ_REG32(DC3_VBI_HOR);
2625 vg_state->vbi_odd_line_enable = READ_REG32(DC3_VBI_LN_ODD);
2626 vg_state->vbi_even_line_enable = READ_REG32(DC3_VBI_LN_EVEN);
2627 vg_state->vbi_pitch = READ_REG32(DC3_VBI_PITCH);
2628 vg_state->color_key = READ_REG32(DC3_COLOR_KEY);
2629 vg_state->color_key_mask = READ_REG32(DC3_COLOR_MASK);
2630 vg_state->color_key_x = READ_REG32(DC3_CLR_KEY_X);
2631 vg_state->color_key_y = READ_REG32(DC3_CLR_KEY_Y);
2632 vg_state->irq = READ_REG32(DC3_IRQ);
2633 vg_state->genlk_ctl = READ_REG32(DC3_GENLK_CTL);
2634 vg_state->vid_y_even_offset = READ_REG32(DC3_VID_EVEN_Y_ST_OFFSET);
2635 vg_state->vid_u_even_offset = READ_REG32(DC3_VID_EVEN_U_ST_OFFSET);
2636 vg_state->vid_v_even_offset = READ_REG32(DC3_VID_EVEN_V_ST_OFFSET);
2637 vg_state->vactive_even = READ_REG32(DC3_V_ACTIVE_EVEN);
2638 vg_state->vblank_even = READ_REG32(DC3_V_BLANK_EVEN);
2639 vg_state->vsync_even = READ_REG32(DC3_V_SYNC_EVEN);
2647 vg_state->palette[i] = READ_REG32(DC3_PAL_DATA);
2661 vg_state->h_coeff[(i << 1)] = READ_REG32(DC3_FILT_COEFF1);
2662 vg_state->h_coeff[(i << 1) + 1] = READ_REG32(DC3_FILT_COEFF2);
2674 vg_state->v_coeff[i] = READ_REG32(DC3_FILT_COEFF1);
2681 vg_state->cursor_data[i] = READ_FB32(offset + (i << 2));
2687 vg_state->pll_flags = 0;
2690 vg_state->dot_pll = CimarronPLLFrequencies[i].frequency;
2699 vg_state->dot_pll = msr_value.high;
2700 vg_state->pll_flags |= VG_PLL_MANUAL;
2703 vg_state->pll_flags |= VG_PLL_DIVIDE_BY_2;
2705 vg_state->pll_flags |= VG_PLL_BYPASS;
2707 vg_state->pll_flags |= VG_PLL_DIVIDE_BY_4;
2709 vg_state->pll_flags |= VG_PLL_VIP_CLOCK;
2713 msr_read64(MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_CAP, &(vg_state->msr_cap));
2715 &(vg_state->msr_config));
2716 msr_read64(MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_SMI, &(vg_state->msr_smi));
2718 &(vg_state->msr_error));
2719 msr_read64(MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_PM, &(vg_state->msr_pm));
2721 &(vg_state->msr_diag));
2722 msr_read64(MSR_DEVICE_GEODELX_VG, DC3_SPARE_MSR, &(vg_state->msr_spare));
2723 msr_read64(MSR_DEVICE_GEODELX_VG, DC3_RAM_CTL, &(vg_state->msr_ram_ctl));
2737 vg_restore_state(VG_SAVE_RESTORE * vg_state)
2748 WRITE_REG32(DC3_PHY_MEM_OFFSET, vg_state->fb_base);
2757 WRITE_REG32(DC3_ARB_CFG, vg_state->arb_cfg);
2758 WRITE_REG32(DC3_FB_ST_OFFSET, vg_state->fb_offset);
2759 WRITE_REG32(DC3_CB_ST_OFFSET, vg_state->cb_offset);
2760 WRITE_REG32(DC3_CURS_ST_OFFSET, vg_state->cursor_offset);
2761 WRITE_REG32(DC3_VID_Y_ST_OFFSET, vg_state->video_y_offset);
2762 WRITE_REG32(DC3_VID_U_ST_OFFSET, vg_state->video_u_offset);
2763 WRITE_REG32(DC3_VID_V_ST_OFFSET, vg_state->video_v_offset);
2764 WRITE_REG32(DC3_DV_TOP, vg_state->dv_top);
2765 WRITE_REG32(DC3_LINE_SIZE, vg_state->line_size);
2766 WRITE_REG32(DC3_GFX_PITCH, vg_state->gfx_pitch);
2767 WRITE_REG32(DC3_VID_YUV_PITCH, vg_state->video_yuv_pitch);
2768 WRITE_REG32(DC3_H_ACTIVE_TIMING, vg_state->h_active);
2769 WRITE_REG32(DC3_H_BLANK_TIMING, vg_state->h_blank);
2770 WRITE_REG32(DC3_H_SYNC_TIMING, vg_state->h_sync);
2771 WRITE_REG32(DC3_V_ACTIVE_TIMING, vg_state->v_active);
2772 WRITE_REG32(DC3_V_BLANK_TIMING, vg_state->v_blank);
2773 WRITE_REG32(DC3_V_SYNC_TIMING, vg_state->v_sync);
2774 WRITE_REG32(DC3_FB_ACTIVE, vg_state->fb_active);
2775 WRITE_REG32(DC3_CURSOR_X, vg_state->cursor_x);
2776 WRITE_REG32(DC3_CURSOR_Y, vg_state->cursor_y);
2777 WRITE_REG32(DC3_VID_DS_DELTA, vg_state->vid_ds_delta);
2778 WRITE_REG32(DC3_PHY_MEM_OFFSET, vg_state->fb_base);
2779 WRITE_REG32(DC3_DV_CTL, vg_state->dv_ctl | 0x00000001);
2780 WRITE_REG32(DC3_GFX_SCALE, vg_state->gfx_scale);
2781 WRITE_REG32(DC3_IRQ_FILT_CTL, vg_state->irq_ctl);
2782 WRITE_REG32(DC3_VBI_EVEN_CTL, vg_state->vbi_even_ctl);
2783 WRITE_REG32(DC3_VBI_ODD_CTL, vg_state->vbi_odd_ctl);
2784 WRITE_REG32(DC3_VBI_HOR, vg_state->vbi_hor_ctl);
2785 WRITE_REG32(DC3_VBI_LN_ODD, vg_state->vbi_odd_line_enable);
2786 WRITE_REG32(DC3_VBI_LN_EVEN, vg_state->vbi_even_line_enable);
2787 WRITE_REG32(DC3_VBI_PITCH, vg_state->vbi_pitch);
2788 WRITE_REG32(DC3_COLOR_KEY, vg_state->color_key);
2789 WRITE_REG32(DC3_COLOR_MASK, vg_state->color_key_mask);
2790 WRITE_REG32(DC3_CLR_KEY_X, vg_state->color_key_x);
2791 WRITE_REG32(DC3_CLR_KEY_Y, vg_state->color_key_y);
2792 WRITE_REG32(DC3_IRQ, vg_state->irq);
2793 WRITE_REG32(DC3_GENLK_CTL, vg_state->genlk_ctl);
2794 WRITE_REG32(DC3_VID_EVEN_Y_ST_OFFSET, vg_state->vid_y_even_offset);
2795 WRITE_REG32(DC3_VID_EVEN_U_ST_OFFSET, vg_state->vid_u_even_offset);
2796 WRITE_REG32(DC3_VID_EVEN_V_ST_OFFSET, vg_state->vid_v_even_offset);
2797 WRITE_REG32(DC3_V_ACTIVE_EVEN, vg_state->vactive_even);
2798 WRITE_REG32(DC3_V_BLANK_EVEN, vg_state->vblank_even);
2799 WRITE_REG32(DC3_V_SYNC_EVEN, vg_state->vsync_even);
2805 WRITE_REG32(DC3_PAL_DATA, vg_state->palette[i]);
2814 WRITE_REG32(DC3_FILT_COEFF1, vg_state->h_coeff[(i << 1)]);
2815 WRITE_REG32(DC3_FILT_COEFF2, vg_state->h_coeff[(i << 1) + 1]);
2824 WRITE_REG32(DC3_FILT_COEFF1, vg_state->v_coeff[i]);
2830 WRITE_FB_STRING32(memoffset, (unsigned char *) &(vg_state->cursor_data[0]),
2836 vg_set_clock_frequency(vg_state->dot_pll, vg_state->pll_flags);
2840 msr_write64(MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_CAP, &(vg_state->msr_cap));
2842 &(vg_state->msr_config));
2843 msr_write64(MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_SMI, &(vg_state->msr_smi));
2845 &(vg_state->msr_error));
2846 msr_write64(MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_PM, &(vg_state->msr_pm));
2848 &(vg_state->msr_diag));
2849 msr_write64(MSR_DEVICE_GEODELX_VG, DC3_SPARE_MSR, &(vg_state->msr_spare));
2850 msr_write64(MSR_DEVICE_GEODELX_VG, DC3_RAM_CTL, &(vg_state->msr_ram_ctl));
2854 WRITE_REG32(DC3_DISPLAY_CFG, vg_state->dcfg);
2855 WRITE_REG32(DC3_GENERAL_CFG, vg_state->gcfg);
2859 WRITE_REG32(DC3_UNLOCK, vg_state->unlock);