Lines Matching refs:READ_REG32
48 unlock = READ_REG32(DC3_UNLOCK);
65 htotal = ((READ_REG32(DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1;
66 hsyncstart = (READ_REG32(DC3_H_SYNC_TIMING) & 0xFFF) + 1;
117 temp = READ_REG32(DC3_VBI_EVEN_CTL) & ~DC3_VBI_EVEN_CTL_OFFSET_MASK;
126 temp = READ_REG32(DC3_VBI_ODD_CTL) & ~DC3_VBI_ODD_CTL_OFFSET_MASK;
152 unlock = READ_REG32(DC3_UNLOCK);
153 temp = READ_REG32(DC3_VBI_EVEN_CTL);
187 unlock = READ_REG32(DC3_UNLOCK);
188 delta = READ_REG32(DC3_VID_DS_DELTA) & DC3_DS_DELTA_MASK;
398 READ_REG32(DC3_VID_DS_DELTA) & DC3_601_VSYNC_SHIFT_MASK;
454 htotal = ((READ_REG32(DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1;
455 hsyncstart = (READ_REG32(DC3_H_SYNC_TIMING) & 0xFFF) + 1;
460 temp = READ_REG32(DC3_VBI_HOR);
482 temp = READ_REG32(DC3_VBI_LN_ODD);
487 temp = READ_REG32(DC3_VBI_LN_EVEN);
495 temp = READ_REG32(DC3_VBI_EVEN_CTL);
503 READ_REG32(DC3_VBI_ODD_CTL) & DC3_VBI_ODD_CTL_OFFSET_MASK;
507 temp = READ_REG32(DC3_VBI_PITCH);
523 if (READ_REG32(DC3_VBI_EVEN_CTL) & DC3_VBI_ENABLE)
542 if (!(READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_TGEN))
577 if (!(READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_TGEN) ||
578 !(READ_REG32(DC3_VBI_EVEN_CTL) & DC3_VBI_ENABLE)) {
582 unlock = READ_REG32(DC3_UNLOCK);
583 gcfg = READ_REG32(DC3_GENERAL_CFG);
584 vbi_even = READ_REG32(DC3_VBI_EVEN_CTL);
597 while (!(READ_REG32(DC3_LINE_CNT_STATUS) & DC3_LNCNT_SIGC));
601 crc = READ_REG32(DC3_PAL_DATA);