Cross Reference: /xsrc/external/mit/xf86-video-geode/dist/src/gfx/vid

Lines Matching refs:msr_value
256     Q_WORD msr_value, sys_value;
285     gfx_msr_read(RC_ID_MCP, MCP_DOTPLL, &msr_value);
296     if ((msr_value.low & MCP_DOTPLL_LOCK) &&
297         (msr_value.high == RCDF_PLLtable[index].pll_value) &&
307     msr_value.high = RCDF_PLLtable[index].pll_value;
308     msr_value.low |= 0x00000001;
309     msr_value.low &= ~MCP_DOTPLL_BYPASS;
310     gfx_msr_write(RC_ID_MCP, MCP_DOTPLL, &msr_value);
320     msr_value.low &= 0xFFFFFFFE;
321     gfx_msr_write(RC_ID_MCP, MCP_DOTPLL, &msr_value);
326         gfx_msr_read(RC_ID_MCP, MCP_DOTPLL, &msr_value);
327     } while (timeout-- && !(msr_value.low & MCP_DOTPLL_LOCK));
1637     Q_WORD msr_value;
1644     gfx_msr_read(RC_ID_MCP, MCP_DOTPLL, &msr_value);
1645     value = msr_value.high & mask;
1649     gfx_msr_read(RC_ID_MCP, MCP_SYS_RSTPLL, &msr_value);
1650     post_div3 = (msr_value.low & MCP_DOTPOSTDIV3) ? 1 : 0;
1651     pre_mult2 = (msr_value.low & MCP_DOTPREMULT2) ? 1 : 0;
2319     Q_WORD msr_value;
2326     gfx_msr_read(RC_ID_DF, RCDF_MBD_MSR_DIAG_DF, &msr_value);
2327     msr_value.low &= ~RCDF_DIAG_32BIT_CRC;
2328     gfx_msr_write(RC_ID_DF, RCDF_MBD_MSR_DIAG_DF, &msr_value);
2368     Q_WORD msr_value;
2375     gfx_msr_read(RC_ID_DF, RCDF_MBD_MSR_DIAG_DF, &msr_value);
2376     msr_value.low |= RCDF_DIAG_32BIT_CRC;
2377     gfx_msr_write(RC_ID_DF, RCDF_MBD_MSR_DIAG_DF, &msr_value);
2418     Q_WORD msr_value;
2427     msr_value.high = 0;
2428     msr_value.low =
2431     gfx_msr_write(RC_ID_DF, MBD_MSR_DIAG, &msr_value);
2436         gfx_msr_read(RC_ID_DF, MBD_MSR_CONFIG, &msr_value);
2437         old_fmt = msr_value.low;
2438         msr_value.low &= ~(RCDF_CONFIG_FMT_MASK);
2439         msr_value.low |=
2442         gfx_msr_write(RC_ID_DF, MBD_MSR_CONFIG, &msr_value);
2447     msr_value.low = MCP_MBD_DIAG_EN1 | 0x00050000;
2448     gfx_msr_write(RC_ID_MCP, MBD_MSR_DIAG, &msr_value);
2452     msr_value.low = 1l;
2453     gfx_msr_write(RC_ID_MCP, MBD_MSR_PM, &msr_value);
2454     msr_value.low = 0;
2455     gfx_msr_write(RC_ID_MCP, MCP_DBGCLKCTL, &msr_value);
2456     msr_value.low = 3;
2457     gfx_msr_write(RC_ID_MCP, MCP_DBGCLKCTL, &msr_value);
2461     msr_value.high = 0x00000000;
2462     msr_value.low = 0x00000000;
2463     gfx_msr_write(RC_ID_MCP, MCP_DIAGCTL, &msr_value);
2508     msr_value.low = 0x000000A0;
2509     msr_value.high = 0x00008000 | ((unsigned long) vsync_bit << 16) |
2511     gfx_msr_write(RC_ID_MCP, vsync_inactive_base, &msr_value);
2516     msr_value.low = 0x000000C0;
2517     gfx_msr_write(RC_ID_MCP, vsync_active_base + 4, &msr_value);
2522     msr_value.low = 0x00000120;
2523     gfx_msr_write(RC_ID_MCP, vsync_inactive_base + 1, &msr_value);
2530     msr_value.high = 0x00008000 | ((unsigned long) hsync_bit << 16) |
2532     msr_value.low = 0x00000120;
2533     gfx_msr_write(RC_ID_MCP, hsync_active_base + 5, &msr_value);
2540     msr_value.high = 0x00000000;
2541     msr_value.low = 0x00000128;
2542     gfx_msr_write(RC_ID_MCP, vsync_inactive_base + 4, &msr_value);
2548     msr_value.high = 0x00000000;
2549     msr_value.low = 0x10C20120;
2550     gfx_msr_write(RC_ID_MCP, vsync_active_base, &msr_value);
2567     msr_value.high = 0x00000000;
2568     msr_value.low = xpos;
2569     gfx_msr_write(RC_ID_MCP, MCP_CMPVAL0, &msr_value);
2574     msr_value.low = xpos + (unsigned long) width;
2575     gfx_msr_write(RC_ID_MCP, MCP_CMPVAL0 + 2, &msr_value);
2585     msr_value.low = ypos << 16;
2586     gfx_msr_write(RC_ID_MCP, MCP_CMPVAL0 + 4, &msr_value);
2591     msr_value.low = (ypos + (unsigned long) height) << 16;
2592     gfx_msr_write(RC_ID_MCP, MCP_CMPVAL0 + 6, &msr_value);
2598     msr_value.high = 0x00000000;
2599     msr_value.low = 0x0000FFFF;
2600     gfx_msr_write(RC_ID_MCP, MCP_CMPMASK0, &msr_value);
2601     gfx_msr_write(RC_ID_MCP, MCP_CMPMASK0 + 2, &msr_value);
2605     msr_value.low = 0xFFFF0000;
2606     gfx_msr_write(RC_ID_MCP, MCP_CMPMASK0 + 4, &msr_value);
2607     gfx_msr_write(RC_ID_MCP, MCP_CMPMASK0 + 6, &msr_value);
2611     msr_value.high = 0x00000000;
2612     msr_value.low = 0x00FFFFFF;
2613     gfx_msr_write(RC_ID_MCP, MCP_REGAMASK, &msr_value);
2620     msr_value.high = 0x00000000;
2621     msr_value.low = 0xFFFF0000 |
2624     gfx_msr_write(RC_ID_MCP, MCP_REGBVAL, &msr_value);
2630     msr_value.high = 0x00000000;
2631     msr_value.low = 0x00000008 | (1l << vsync_inactive_shift);
2632     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 14, &msr_value);
2636     msr_value.low = 0x00080000 | (1l << (vsync_active_shift + 16));
2637     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 15, &msr_value);
2641     msr_value.low = 0x00000080 | (1l << (vsync_inactive_shift + 4));
2642     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 16, &msr_value);
2648     msr_value.low = 0x00080000 | (1l << (vsync_active_shift + 16));
2649     gfx_msr_write(RC_ID_MCP, MCP_ACTION0, &msr_value);
2657     msr_value.low = 0x00000008 | (1l << vsync_active_shift) |
2659     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 1, &msr_value);
2665     msr_value.low = 0x00080000 | (1l << (vsync_inactive_shift + 16));
2666     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 2, &msr_value);
2671     msr_value.low = 0x00000000;
2672     msr_value.high = 0x00000000;
2673     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 3, &msr_value);
2674     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 4, &msr_value);
2675     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 5, &msr_value);
2676     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 6, &msr_value);
2677     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 7, &msr_value);
2678     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 8, &msr_value);
2679     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 9, &msr_value);
2680     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 10, &msr_value);
2681     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 11, &msr_value);
2682     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 12, &msr_value);
2683     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 13, &msr_value);
2684     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 17, &msr_value);
2685     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 18, &msr_value);
2686     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 19, &msr_value);
2687     gfx_msr_write(RC_ID_MCP, MCP_ACTION0 + 20, &msr_value);
2692         msr_value.low = 0x00000001;
2693     gfx_msr_write(RC_ID_MCP, MCP_REGA, &msr_value);
2697     msr_value.low = 0;
2698     msr_value.high = 0;
2699     gfx_msr_write(RC_ID_MCP, MCP_XSTATE, &msr_value);
2709         msr_value.low = 0x9A820055;
2711         msr_value.low = 0x9A840055;
2712     msr_value.high = 0x00000000;
2713     gfx_msr_write(RC_ID_MCP, MCP_DIAGCTL, &msr_value);
2725     gfx_msr_read(RC_ID_MCP, MCP_XSTATE, &msr_value);
2726     if ((msr_value.low & 3) == 3) {
2727         gfx_msr_read(RC_ID_MCP, MCP_REGA, &msr_value);
2729         crc = msr_value.low;
2736     msr_value.low = 0x00000000;
2737     msr_value.high = 0x00000000;
2738     gfx_msr_write(RC_ID_DF, MBD_MSR_DIAG, &msr_value);
2739     gfx_msr_write(RC_ID_MCP, MBD_MSR_DIAG, &msr_value);
2743     msr_value.high = 0x00000000;
2744     msr_value.low = 0x00000000;
2745     gfx_msr_write(RC_ID_MCP, MCP_DIAGCTL, &msr_value);
2750         gfx_msr_read(RC_ID_DF, MBD_MSR_CONFIG, &msr_value);
2751         msr_value.low = old_fmt;
2752         gfx_msr_write(RC_ID_DF, MBD_MSR_CONFIG, &msr_value);