Lines Matching defs:i810Reg
1077 DoSave(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, I810RegPtr i810Reg,
1100 i810Reg->IOControl = hwp->readCrtc(hwp, IO_CTNL);
1101 i810Reg->AddressMapping = pI810->readControl(pI810, GRX, ADDRESS_MAPPING);
1102 i810Reg->BitBLTControl = INREG8(BITBLT_CNTL);
1103 i810Reg->VideoClk2_M = INREG16(VCLK2_VCO_M);
1104 i810Reg->VideoClk2_N = INREG16(VCLK2_VCO_N);
1105 i810Reg->VideoClk2_DivisorSel = INREG8(VCLK2_VCO_DIV_SEL);
1107 i810Reg->ExtVertTotal = hwp->readCrtc(hwp, EXT_VERT_TOTAL);
1108 i810Reg->ExtVertDispEnd = hwp->readCrtc(hwp, EXT_VERT_DISPLAY);
1109 i810Reg->ExtVertSyncStart = hwp->readCrtc(hwp, EXT_VERT_SYNC_START);
1110 i810Reg->ExtVertBlankStart = hwp->readCrtc(hwp, EXT_VERT_BLANK_START);
1111 i810Reg->ExtHorizTotal = hwp->readCrtc(hwp, EXT_HORIZ_TOTAL);
1112 i810Reg->ExtHorizBlank = hwp->readCrtc(hwp, EXT_HORIZ_BLANK);
1113 i810Reg->ExtOffset = hwp->readCrtc(hwp, EXT_OFFSET);
1114 i810Reg->InterlaceControl = hwp->readCrtc(hwp, INTERLACE_CNTL);
1116 i810Reg->PixelPipeCfg0 = INREG8(PIXPIPE_CONFIG_0);
1117 i810Reg->PixelPipeCfg1 = INREG8(PIXPIPE_CONFIG_1);
1118 i810Reg->PixelPipeCfg2 = INREG8(PIXPIPE_CONFIG_2);
1119 i810Reg->DisplayControl = INREG8(DISPLAY_CNTL);
1120 i810Reg->LMI_FIFO_Watermark = INREG(FWATER_BLC);
1123 i810Reg->Fence[i] = INREG(FENCE + i * 4);
1125 i810Reg->LprbTail = INREG(LP_RING + RING_TAIL);
1126 i810Reg->LprbHead = INREG(LP_RING + RING_HEAD);
1127 i810Reg->LprbStart = INREG(LP_RING + RING_START);
1128 i810Reg->LprbLen = INREG(LP_RING + RING_LEN);
1130 if ((i810Reg->LprbTail & TAIL_ADDR) != (i810Reg->LprbHead & HEAD_ADDR) &&
1131 i810Reg->LprbLen & RING_VALID) {
1218 DoRestore(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, I810RegPtr i810Reg,
1232 i810PrintMode(vgaReg, i810Reg);
1248 OUTREG16(VCLK2_VCO_M, i810Reg->VideoClk2_M);
1249 OUTREG16(VCLK2_VCO_N, i810Reg->VideoClk2_N);
1250 OUTREG8(VCLK2_VCO_DIV_SEL, i810Reg->VideoClk2_DivisorSel);
1263 temp |= (i810Reg->PixelPipeCfg0 & DAC_8_BIT);
1275 * if (i810Reg->std.NoClock >= 0)
1283 hwp->writeCrtc(hwp, EXT_VERT_TOTAL, i810Reg->ExtVertTotal);
1284 hwp->writeCrtc(hwp, EXT_VERT_DISPLAY, i810Reg->ExtVertDispEnd);
1285 hwp->writeCrtc(hwp, EXT_VERT_SYNC_START, i810Reg->ExtVertSyncStart);
1286 hwp->writeCrtc(hwp, EXT_VERT_BLANK_START, i810Reg->ExtVertBlankStart);
1287 hwp->writeCrtc(hwp, EXT_HORIZ_TOTAL, i810Reg->ExtHorizTotal);
1288 hwp->writeCrtc(hwp, EXT_HORIZ_BLANK, i810Reg->ExtHorizBlank);
1289 hwp->writeCrtc(hwp, EXT_OFFSET, i810Reg->ExtOffset);
1293 temp |= i810Reg->InterlaceControl;
1298 temp |= i810Reg->AddressMapping;
1313 ActiveStart = i810Reg->OverlayActiveStart;
1314 ActiveEnd = i810Reg->OverlayActiveEnd;
1328 temp |= i810Reg->BitBLTControl;
1333 temp |= i810Reg->DisplayControl;
1338 temp |= i810Reg->PixelPipeCfg0;
1343 temp |= i810Reg->PixelPipeCfg2;
1349 temp |= i810Reg->PixelPipeCfg1;
1357 itemp |= i810Reg->LMI_FIFO_Watermark;
1361 OUTREG(FENCE + i * 4, i810Reg->Fence[i]);
1363 ErrorF("Fence Register : %x\n", i810Reg->Fence[i]);
1383 itemp |= i810Reg->LprbStart;
1388 itemp |= i810Reg->LprbLen;
1404 temp |= i810Reg->IOControl;
1457 I810RegPtr i810Reg = &pI810->ModeReg;
1498 i810Reg->VideoClk2_M = (m_best - 2) & 0x3FF;
1499 i810Reg->VideoClk2_N = (n_best - 2) & 0x3FF;
1500 i810Reg->VideoClk2_DivisorSel = (p_best << 4);
1505 i810Reg->VideoClk2_M, i810Reg->VideoClk2_N,
1506 i810Reg->VideoClk2_DivisorSel, m_best, n_best, p_best);
1513 I810RegPtr i810Reg = &pI810->ModeReg;
1520 i810Reg->ExtOffset = pScrn->displayWidth >> 11;
1521 i810Reg->PixelPipeCfg1 = DISPLAY_8BPP_MODE;
1522 i810Reg->BitBLTControl = COLEXP_8BPP;
1526 i810Reg->PixelPipeCfg1 = DISPLAY_15BPP_MODE;
1528 i810Reg->PixelPipeCfg1 = DISPLAY_16BPP_MODE;
1531 i810Reg->ExtOffset = pScrn->displayWidth >> 10;
1532 i810Reg->BitBLTControl = COLEXP_16BPP;
1535 i810Reg->PixelPipeCfg2 = DISPLAY_GAMMA_ENABLE;
1539 i810Reg->ExtOffset = (pScrn->displayWidth * 3) >> 11;
1541 i810Reg->PixelPipeCfg1 = DISPLAY_24BPP_MODE;
1542 i810Reg->BitBLTControl = COLEXP_24BPP;
1545 i810Reg->PixelPipeCfg2 = DISPLAY_GAMMA_ENABLE;
1553 i810Reg->PixelPipeCfg0 = DAC_6_BIT;
1555 i810Reg->PixelPipeCfg0 = DAC_8_BIT;
1558 i810Reg->PixelPipeCfg1 |= 0x10;
1561 i810Reg->IOControl = EXTENDED_CRTC_CNTL;
1564 i810Reg->AddressMapping = (LINEAR_MODE_ENABLE | GTT_MEM_MAP_ENABLE);
1567 i810Reg->DisplayControl = HIRES_MODE;
1570 i810Reg->ExtVertTotal = (mode->CrtcVTotal - 2) >> 8;
1571 i810Reg->ExtVertDispEnd = (mode->CrtcVDisplay - 1) >> 8;
1572 i810Reg->ExtVertSyncStart = mode->CrtcVSyncStart >> 8;
1573 i810Reg->ExtVertBlankStart = mode->CrtcVBlankStart >> 8;
1574 i810Reg->ExtHorizTotal = ((mode->CrtcHTotal >> 3) - 5) >> 8;
1575 i810Reg->ExtHorizBlank = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x40) >> 6;
1589 i810Reg->ExtHorizBlank = vgaHWHBlankKGA(mode, pVga, 7, 0);
1596 if ((mode->CrtcVDisplay == 768) && (i810Reg->ExtVertBlankStart == 3)) {
1597 i810Reg->ExtVertBlankStart = 2;
1599 if ((mode->CrtcVDisplay == 1024) && (i810Reg->ExtVertBlankStart == 4)) {
1600 i810Reg->ExtVertBlankStart = 3;
1604 i810Reg->OverlayActiveStart = mode->CrtcHTotal - 32;
1605 i810Reg->OverlayActiveEnd = mode->CrtcHDisplay - 32;
1609 i810Reg->InterlaceControl = INTERLACE_ENABLE;
1610 i810Reg->ExtVertDispEnd *= 2;
1612 i810Reg->InterlaceControl = INTERLACE_DISABLE;
1630 i810Reg->LMI_FIFO_Watermark = I810CalcWatermark(pScrn, dclk, FALSE);
1633 i810Reg->LprbTail = 0;
1634 i810Reg->LprbHead = 0;
1635 i810Reg->LprbStart = pI810->LpRing->mem.Start;
1637 if (i810Reg->LprbStart)
1638 i810Reg->LprbLen = ((pI810->LpRing->mem.Size - 4096) |
1641 i810Reg->LprbLen = RING_INVALID;
1935 I810RegPtr i810Reg = &pI810->ModeReg;
1939 i810Reg->Fence[i] = 0;