Lines Matching refs:clock
459 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
461 static void i8xx_clock(int refclk, intel_clock_t *clock)
463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
469 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
471 static void i9xx_clock(int refclk, intel_clock_t *clock)
473 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
474 clock->p = clock->p1 * clock->p2;
475 clock->vco = refclk * clock->m / (clock->n + 2);
476 clock->dot = clock->vco / clock->p;
480 static void igd_clock(int refclk, intel_clock_t *clock)
482 clock->m = clock->m2 + 2;
483 clock->p = clock->p1 * clock->p2;
484 clock->vco = refclk * clock->m / clock->n;
485 clock->dot = clock->vco / clock->p;
488 static void intel_clock(I830Ptr pI830, int refclk, intel_clock_t *clock)
492 igd_clock(refclk, clock);
494 i9xx_clock (refclk, clock);
496 i8xx_clock (refclk, clock);
500 i830PrintPll(ScrnInfoPtr pScrn, char *prefix, intel_clock_t *clock)
505 prefix, clock->dot, clock->vco,
506 clock->m, clock->m1, clock->m2,
507 clock->n,
508 clock->p, clock->p1, clock->p2);
541 i830PllIsValid(xf86CrtcPtr crtc, intel_clock_t *clock)
547 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
549 if (clock->p < limit->p.min || limit->p.max < clock->p)
551 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
553 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
555 if (clock->m1 <= clock->m2 && !IS_IGD(pI830))
557 if (clock->m < limit->m.min || limit->m.max < clock->m)
559 if (clock->n < limit->n.min || limit->n.max < clock->n)
561 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
563 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 intel_clock_t clock;
588 clock.p2 = limit->p2.p2_fast;
590 clock.p2 = limit->p2.p2_slow;
593 clock.p2 = limit->p2.p2_slow;
595 clock.p2 = limit->p2.p2_fast;
600 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++)
602 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++)
605 if (clock.m2 >= clock.m1 && !IS_IGD(pI830))
607 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++)
609 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; clock.p1++)
613 intel_clock (pI830, refclk, &clock);
615 if (!i830PllIsValid(crtc, &clock))
618 this_err = abs(clock.dot - target);
620 *best_clock = clock;
636 intel_clock_t clock;
648 clock.p2 = limit->p2.p2_fast;
650 clock.p2 = limit->p2.p2_slow;
653 clock.p2 = limit->p2.p2_slow;
655 clock.p2 = limit->p2.p2_fast;
660 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
662 for (clock.m1 = limit->m1.max;
663 clock.m1 >= limit->m1.min; clock.m1--) {
664 for (clock.m2 = limit->m2.max;
665 clock.m2 >= limit->m2.min; clock.m2--) {
666 for (clock.p1 = limit->p1.max;
667 clock.p1 >= limit->p1.min; clock.p1--) {
670 intel_clock (pI830, refclk, &clock);
671 if (!i830PllIsValid(crtc, &clock))
673 this_err = abs(clock.dot - target) ;
675 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 max_n = clock.n;
1338 /** Returns the core display clock speed for i830 - i945 */
1344 /* Core clock values taken from the published datasheets.
1519 intel_clock_t clock;
1569 "using SSC reference clock of %d MHz\n", refclk / 1000);
1577 * Returns a set of divisors for the desired target clock with the given
1578 * refclk, or FALSE. The returned values represent the clock equation:
1582 ok = limit->find_pll(limit, crtc, adjusted_mode->Clock, refclk, &clock);
1586 if (fabs(adjusted_mode->Clock - clock.dot) / clock.dot > .02) {
1588 "Chosen PLL clock of %.1f Mhz more than 2%% away from "
1590 (float)clock.dot / 1000,
1594 /* SDVO TV has fixed PLL values depends on its clock range,
1599 clock.p1 = 2;
1600 clock.p2 = 10;
1601 clock.n = 3;
1602 clock.m1 = 16;
1603 clock.m2 = 8;
1606 clock.p1 = 1;
1607 clock.p2 = 10;
1608 clock.n = 6;
1609 clock.m1 = 12;
1610 clock.m2 = 8;
1615 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1617 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1637 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1639 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1640 switch (clock.p2) {
1658 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1660 if (clock.p1 == 2)
1663 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1664 if (clock.p2 == 4)
1712 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1748 i830PrintPll(pScrn, "chosen", &clock);
1771 if (clock.p2 == I9XX_P2_LVDS_FAST)
2193 /* Returns the clock of the currently programmed mode of the given pipe. */
2202 intel_clock_t clock;
2209 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2211 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2212 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2214 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2215 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2219 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2222 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2227 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
2230 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
2240 intel_clock(pI830, 100000, &clock);
2242 intel_clock(pI830, 96000, &clock);
2247 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2252 clock.p2 = 7;
2254 clock.p2 = 14;
2257 intel_clock(pI830, 66000, &clock); /* XXX: might not be 66MHz */
2259 intel_clock(pI830, 48000, &clock);
2262 clock.p1 = 2;
2264 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2268 clock.p2 = 4;
2270 clock.p2 = 2;
2272 intel_clock(pI830, 48000, &clock);
2281 i830PrintPll(pScrn, "probed", &clock);
2283 return clock.dot;