Cross Reference: /xsrc/external/mit/xf86-video-intel-old/dist/src/i830

Lines Matching refs:INREG
787 	    OUTREG(TV_CTL, INREG(TV_CTL) | TV_ENC_ENABLE);
792 	    OUTREG(TV_CTL, INREG(TV_CTL) & ~TV_ENC_ENABLE);
807     dev_priv->save_TV_H_CTL_1 = INREG(TV_H_CTL_1);
808     dev_priv->save_TV_H_CTL_2 = INREG(TV_H_CTL_2);
809     dev_priv->save_TV_H_CTL_3 = INREG(TV_H_CTL_3);
810     dev_priv->save_TV_V_CTL_1 = INREG(TV_V_CTL_1);
811     dev_priv->save_TV_V_CTL_2 = INREG(TV_V_CTL_2);
812     dev_priv->save_TV_V_CTL_3 = INREG(TV_V_CTL_3);
813     dev_priv->save_TV_V_CTL_4 = INREG(TV_V_CTL_4);
814     dev_priv->save_TV_V_CTL_5 = INREG(TV_V_CTL_5);
815     dev_priv->save_TV_V_CTL_6 = INREG(TV_V_CTL_6);
816     dev_priv->save_TV_V_CTL_7 = INREG(TV_V_CTL_7);
817     dev_priv->save_TV_SC_CTL_1 = INREG(TV_SC_CTL_1);
818     dev_priv->save_TV_SC_CTL_2 = INREG(TV_SC_CTL_2);
819     dev_priv->save_TV_SC_CTL_3 = INREG(TV_SC_CTL_3);
821     dev_priv->save_TV_CSC_Y = INREG(TV_CSC_Y);
822     dev_priv->save_TV_CSC_Y2 = INREG(TV_CSC_Y2);
823     dev_priv->save_TV_CSC_U = INREG(TV_CSC_U);
824     dev_priv->save_TV_CSC_U2 = INREG(TV_CSC_U2);
825     dev_priv->save_TV_CSC_V = INREG(TV_CSC_V);
826     dev_priv->save_TV_CSC_V2 = INREG(TV_CSC_V2);
827     dev_priv->save_TV_CLR_KNOBS = INREG(TV_CLR_KNOBS);
828     dev_priv->save_TV_CLR_LEVEL = INREG(TV_CLR_LEVEL);
829     dev_priv->save_TV_WIN_POS = INREG(TV_WIN_POS);
830     dev_priv->save_TV_WIN_SIZE = INREG(TV_WIN_SIZE);
831     dev_priv->save_TV_FILTER_CTL_1 = INREG(TV_FILTER_CTL_1);
832     dev_priv->save_TV_FILTER_CTL_2 = INREG(TV_FILTER_CTL_2);
833     dev_priv->save_TV_FILTER_CTL_3 = INREG(TV_FILTER_CTL_3);
836 	dev_priv->save_TV_H_LUMA[i] = INREG(TV_H_LUMA_0 + (i <<2));
838 	dev_priv->save_TV_H_CHROMA[i] = INREG(TV_H_CHROMA_0 + (i <<2));
840 	dev_priv->save_TV_V_LUMA[i] = INREG(TV_V_LUMA_0 + (i <<2));
842 	dev_priv->save_TV_V_CHROMA[i] = INREG(TV_V_CHROMA_0 + (i <<2));
844     dev_priv->save_TV_DAC = INREG(TV_DAC);
845     dev_priv->save_TV_CTL = INREG(TV_CTL);
888 	int pipeconf = INREG(pipeconf_reg);
889 	int dspcntr = INREG(dspcntr_reg);
894 	OUTREG(dspbase_reg, INREG(dspbase_reg));
914 	OUTREG(dspbase_reg, INREG(dspbase_reg));
1062     uint32_t val = INREG(TV_CLR_KNOBS) & ~TV_BRIGHTNESS_MASK;
1072     uint32_t val = INREG(TV_CLR_KNOBS) & ~TV_CONTRAST_MASK;;
1092     uint32_t val = INREG(TV_CLR_KNOBS) & ~TV_SATURATION_MASK;
1111     uint32_t val = INREG(TV_CLR_KNOBS) & ~TV_HUE_MASK;
1140     tv_ctl = INREG(TV_CTL);
1283 	int pipeconf = INREG(pipeconf_reg);
1284 	int dspcntr = INREG(dspcntr_reg);
1291 	OUTREG(dspbase_reg, INREG(dspbase_reg));
1322 	OUTREG(dspbase_reg, INREG(dspbase_reg));
1375     tv_dac = INREG(TV_DAC);
1383 	tv_ctl = INREG(TV_CTL);
1403 	tv_dac = INREG(TV_DAC);
1908     int pipe = !!(INREG(TV_CTL) & TV_ENC_PIPEB_SELECT);
1950     if ((INREG(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1957     save_tv_dac = INREG(TV_DAC);
1960     tv_dac_on = INREG(TV_DAC);
1963     tv_dac_off = INREG(TV_DAC);