Cross Reference: /xsrc/external/mit/xf86-video-mach64/dist/src/atidsp.c

Lines Matching defs:pATI
42     ATIPtr pATI
52     pATI->ClockDescriptor.NumD = 8;
56     pATI->XCLKPostDivider = GetBits(IOValue, PLL_XCLK_SRC_SEL);
57     pATI->XCLKReferenceDivider = 1;
58     switch (pATI->XCLKPostDivider)
64             pATI->XCLKReferenceDivider = 3;
65             pATI->XCLKPostDivider = 0;
70                 "Unsupported XCLK source:  %d.\n", pATI->XCLKPostDivider);
74     pATI->XCLKPostDivider -= GetBits(IOValue, PLL_MFB_TIMES_4_2B);
75     pATI->XCLKFeedbackDivider = ATIMach64GetPLLReg(PLL_MCLK_FB_DIV);
79         ATIDivide(pATI->XCLKFeedbackDivider * pATI->ReferenceNumerator,
80                   pATI->XCLKReferenceDivider * pATI->ClockDescriptor.MaxM *
81                   pATI->ReferenceDenominator, 1 - pATI->XCLKPostDivider, 0) /
83         GetBits(pATI->LockData.mem_cntl, CTL_MEM_REFRESH_RATE_B));
86     trp = GetBits(pATI->LockData.mem_cntl, CTL_MEM_TRP);
87     pATI->XCLKPageFaultDelay = GetBits(pATI->LockData.mem_cntl, CTL_MEM_TRCD) +
88         GetBits(pATI->LockData.mem_cntl, CTL_MEM_TCRD) + trp + 2;
89     pATI->XCLKMaxRASDelay = GetBits(pATI->LockData.mem_cntl, CTL_MEM_TRAS) +
91     pATI->DisplayFIFODepth = 32;
93     if (pATI->Chip < ATI_CHIP_264VT4)
95         pATI->XCLKPageFaultDelay += 2;
96         pATI->XCLKMaxRASDelay += 3;
97         pATI->DisplayFIFODepth = 24;
100     switch (pATI->MemoryType)
103             if (pATI->VideoRAM <= 1024)
105                 pATI->DisplayLoopLatency = 10;
109                 pATI->DisplayLoopLatency = 8;
110                 pATI->XCLKPageFaultDelay += 2;
116             if (pATI->VideoRAM <= 1024)
118                 pATI->DisplayLoopLatency = 9;
122                 pATI->DisplayLoopLatency = 8;
123                 pATI->XCLKPageFaultDelay++;
128             if (pATI->VideoRAM <= 1024)
130                 pATI->DisplayLoopLatency = 11;
134                 pATI->DisplayLoopLatency = 10;
135                 pATI->XCLKPageFaultDelay++;
140             pATI->DisplayLoopLatency = 8;
141             pATI->XCLKPageFaultDelay += 3;
145             pATI->DisplayLoopLatency = 11;
146             pATI->XCLKPageFaultDelay += 3;
150     if (pATI->XCLKMaxRASDelay <= pATI->XCLKPageFaultDelay)
151         pATI->XCLKMaxRASDelay = pATI->XCLKPageFaultDelay + 1;
160         pATI->DisplayLoopLatency = GetBits(dsp_config, DSP_LOOP_LATENCY);
162     if ((!dsp_on_off && (pATI->Chip < ATI_CHIP_264GTPRO)) ||
168             pATI->DisplayFIFODepth = 32;
170             pATI->DisplayFIFODepth = 24;
185     ATIPtr   pATI,
207     ATIPtr         pATI,
213     int RASMultiplier = pATI->XCLKMaxRASDelay, RASDivider = 1;
220     Multiplier = pATI->XCLKFeedbackDivider *
221         pATI->ClockDescriptor.PostDividers[pATIHW->PostDivider];
222     Divider = pATIHW->FeedbackDivider * pATI->XCLKReferenceDivider;
225         Divider *= pATI->bitsPerPixel / 4;
229     vshift = (6 - 2) - pATI->XCLKPostDivider;
231     if (pATI->OptionPanelDisplay && (pATI->LCDPanelID >= 0))
234         Multiplier *= pATI->LCDHorizontal;
237         RASMultiplier *= pATI->LCDHorizontal;
242     tmp = ATIDivide(Multiplier * pATI->DisplayFIFODepth, Divider, vshift, -1);
254     dsp_off = ATIDivide(Multiplier * (pATI->DisplayFIFODepth - 1), Divider,
264             ATIDivide(pATI->XCLKPageFaultDelay, 1, xshift, 1);
285         SetBits(pATI->DisplayLoopLatency, DSP_LOOP_LATENCY);
296     ATIPtr   pATI,