Lines Matching refs:save
57 Bool R128InitCrtcRegisters(xf86CrtcPtr crtc, R128SavePtr save, DisplayModePtr mode)
92 save->crtc_gen_cntl = (R128_CRTC_EXT_DISP_EN
106 save->crtc_gen_cntl &= ~(R128_CRTC_DBL_SCAN_EN | R128_CRTC_INTERLACE_EN);
108 save->crtc_ext_cntl |= R128_VGA_ATI_LINEAR | R128_XCRT_CNT_EN;
110 save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0xffff)
119 save->crtc_h_sync_strt_wid = ((hsync_start & 0xfff)
127 save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
132 save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
142 save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
147 save->crtc_pitch = info->CurrentLayout.displayWidth / 8;
152 save->crtc_pitch, pScrn->virtualX,
159 case 16: save->config_cntl |= APER_0_BIG_ENDIAN_16BPP_SWAP; break;
160 case 32: save->config_cntl |= APER_0_BIG_ENDIAN_32BPP_SWAP; break;
169 Bool R128InitCrtc2Registers(xf86CrtcPtr crtc, R128SavePtr save, DisplayModePtr mode)
196 save->crtc2_gen_cntl = (R128_CRTC2_EN
202 save->crtc2_gen_cntl &= ~R128_CRTC_EXT_DISP_EN;
203 save->crtc2_gen_cntl |= (1 << 21);
205 save->crtc2_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0xffff)
214 save->crtc2_h_sync_strt_wid = ((hsync_start & 0xfff)
222 save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
227 save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
237 save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
242 save->crtc2_pitch = info->CurrentLayout.displayWidth / 8;
247 save->crtc2_pitch, pScrn->virtualX,
290 static Bool R128InitCrtcBase(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
312 save->crtc_offset = Base;
313 save->crtc_offset_cntl = 0;
318 static Bool R128InitCrtc2Base(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
340 save->crtc2_offset = Base;
341 save->crtc2_offset_cntl = 0;
347 static void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save,
379 save->pll_output_freq = post_div->divider * freq;
380 if (save->pll_output_freq >= pll->min_pll_freq
381 && save->pll_output_freq <= pll->max_pll_freq) break;
384 save->dot_clock_freq = freq;
385 save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
387 save->post_div = post_div->divider;
391 save->dot_clock_freq,
392 save->pll_output_freq,
393 save->feedback_div,
394 save->post_div));
396 save->ppll_ref_div = pll->reference_div;
397 save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
398 save->htotal_cntl = 0;
403 void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save,
435 save->pll_output_freq_2 = post_div->divider * freq;
436 if (save->pll_output_freq_2 >= pll->min_pll_freq
437 && save->pll_output_freq_2 <= pll->max_pll_freq) break;
440 save->dot_clock_freq_2 = freq;
441 save->feedback_div_2 = R128Div(pll->reference_div
442 * save->pll_output_freq_2,
444 save->post_div_2 = post_div->divider;
448 save->dot_clock_freq_2,
449 save->pll_output_freq_2,
450 save->feedback_div_2,
451 save->post_div_2));
453 save->p2pll_ref_div = pll->reference_div;
454 save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16));
455 save->htotal_cntl2 = 0;
640 Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save,
660 VclkFreq = R128Div(pll->reference_freq * save->feedback_div,
661 pll->reference_div * save->post_div);
694 save->dda_config = (XclksPerTransferPrecise
698 save->dda_on_off = (Ron << 16) | Roff;
716 Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save,
736 VclkFreq = R128Div(pll->reference_freq * save->feedback_div_2,
737 pll->reference_div * save->post_div_2);
771 save->dda2_config = (XclksPerTransferPrecise
775 /*save->dda2_on_off = (Ron << 16) | Roff;*/
777 save->dda2_on_off = (Ron << 18) | Roff;
1061 .save = NULL,