Lines Matching defs:clock
104 save->clock.value = READ_SCR(pSmi, save->current_clock);
207 mode->clock.f.m_select = x_select;
208 mode->clock.f.m_divider = x_divider;
209 mode->clock.f.m_shift = x_shift;
217 mode->clock.f.m1_select = x_select;
218 mode->clock.f.m1_divider = x_divider;
219 mode->clock.f.m1_shift = x_shift;
240 MSOCClockRec clock;
247 clock.value = READ_SCR(pSmi, mode->current_clock);
250 clock.f.m_select = mode->clock.f.m_select;
251 pll = clock.value;
252 clock.f.m_divider = mode->clock.f.m_divider;
253 clock.f.m_shift = mode->clock.f.m_shift;
254 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
258 clock.f.m1_select = mode->clock.f.m1_select;
259 pll = clock.value;
260 clock.f.m1_divider = mode->clock.f.m1_divider;
261 clock.f.m1_shift = mode->clock.f.m1_shift;
262 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
287 MSOCClockRec clock;
291 clock.value = READ_SCR(pSmi, mode->current_clock);
295 if (mode->clock.f.pll_select)
297 clock.f.p2_select = mode->clock.f.p2_select;
298 pll = clock.value;
299 clock.f.p2_divider = mode->clock.f.p2_divider;
300 clock.f.p2_shift = mode->clock.f.p2_shift;
301 clock.f.pll_select = mode->clock.f.pll_select;
302 clock.f.p2_1xclck = mode->clock.f.p2_1xclck;
303 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
326 MSOCClockRec clock;
330 clock.value = READ_SCR(pSmi, mode->current_clock);
332 clock.f.v2_select = mode->clock.f.v2_select;
333 pll = clock.value;
334 clock.f.v2_divider = mode->clock.f.v2_divider;
335 clock.f.v2_shift = mode->clock.f.v2_shift;
336 clock.f.v2_1xclck = mode->clock.f.v2_1xclck;
337 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
451 SMI501_FindClock(double clock, int32_t max_divider, Bool has1xclck,
462 /* Find clock best matching mode */
471 diff = (mclk / (divider << shift << xclck)) - clock;
487 "\tMatching clock %5.2f, diff %5.2f (%d/%d/%d/%d)\n",
497 SMI501_FindMemClock(double clock, int32_t *x1_select,
509 diff = (mclk / (divider << shift)) - clock;
523 "\tMatching clock %5.2f, diff %5.2f (%d/%d/%d)\n",
533 SMI501_FindPLLClock(double clock, int32_t *m, int32_t *n, int32_t *xclck)
542 * pixel clock, with the actual pixel clock that can be achieved by
563 * where requested_clock is modeline pixel clock,
572 M = clock / frequency * K * N;
573 diff = ((int32_t)(frequency / K * M) / N) - clock;
587 "\tMatching alternate clock %5.2f, diff %5.2f (%d/%d/%d)\n",
642 * 1. There should be only one clock source changed at a time.
643 * To change clock source for P2XCLK, V2XCLK, MCLK, M2XCLK
646 * change one clock source to another.
647 * 2. When adjusting the clock rate, the PLL selection bit should
649 * clock source. For example, to change the P2XCLK clock rate:
654 * before the clock rate is changed.
655 * 3. There should be a minimum 16 ms wait after a clock source is
660 /* register contents selecting clock */