Cross Reference: /xsrc/external/mit/xf86-video-sis/dist/src/init301.c

Lines Matching defs:tempbl
2480   unsigned short tempbl;
2509 	   tempbl = SiS_GetReg(SiS_Pr->SiS_P3c4,0x32);
2510 	   tempbl &= 0xef;
2511 	   tempbl |= 0x02;
2513 	      tempbl |= 0x10;
2514 	      tempbl &= 0xfd;
2516 	   SiS_SetReg(SiS_Pr->SiS_P3c4,0x32,tempbl);
2693 	   tempbl = 0xfb;
2697 	         tempbl = 0xff;
2700 	   SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,tempbl,tempah);
2714 	   tempbl = 0xc0;
2718 	      tempbl = 0x00;
2721 	   SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x21,0x3f,tempbl);
2731 	   tempbl = 0xcf; tempbl2 = 0x3f;
2740 	   SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2c,tempbl,tempah);
2744 	   tempbl = 0xcf; tempbl2 = 0x3f;
2748 		 tempbl = tempbl2 = 0xff;
2751 	   SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2c,tempbl,tempah);
2761 	   tempbl = 0x7f;
2763 	      tempbl = 0xff;
2766 	   SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x23,tempbl,tempah);
2802 	   tempbl = 0xfb;
2805 	      if(SiS_IsDualEdge(SiS_Pr)) tempbl = 0xff;
2807 	   SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,tempbl,tempah);
4978    unsigned short tempah=0, tempbl, infoflag;
4980    tempbl = 0xC0;
5037 	    tempbl = 0;
5041 		  tempbl = (tempah >> 6) & 0x03;
5050 	       SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1a,0xf0,tempbl);
5069 	    tempbl = 0;
5074 		 tempbl = ((SiS_Pr->SiS_LCDInfo & 0xc0) >> 6);
5079 	       tempbl = 0x03;
5082 	       tempbl = (tempah >> 6) & 0x03;
5083 	       tempbl |= 0x08;
5084 	       if(!(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit)) tempbl |= 0x04;
5093 		  SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1a,0xf0,tempbl);
5099 	    tempah = tempbl = infoflag >> 8;
5101 	       tempbl = 0;
5111 		       tempbl = (tempah >> 6) & 0x03;
5131 		     SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1a,0xf0,tempbl);
6082   unsigned short  tempbl=0;
6395 	      tempbl = 0xF0;
6398 		    if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) tempbl = 0x0F;
6404 		 tempbl = 0;
6406 		    if(ROMAddr[0x13c] & 0x80) tempbl = 0xf0;
6410 	      SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2D,tempbl,temp);	    /* Panel Link Delay Compensation */
9143   unsigned short tempbl;
9145   tempbl = (SiS_GetCH70xx(SiS_Pr, (reg & 0xFF)) & myand) | myor;
9146   SiS_SetCH70xx(SiS_Pr, reg, tempbl);
10671   unsigned short tempcl,tempch,tempbl,tempbh,tempbx,tempax,temp;
10841 	tempbl = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x04);
10842 	tempbx = (tempbh << 8) | tempbl;