Lines Matching defs:regp
1752 SiS_HBlankKGA(DisplayModePtr mode, SISRegPtr regp, int nBits, unsigned int Flags)
1758 regp->sisRegs3D4[3] = (regp->sisRegs3D4[3] & ~0x1F) |
1760 regp->sisRegs3D4[5] = (regp->sisRegs3D4[5] & ~0x80) |
1766 int i = (regp->sisRegs3D4[3] & 0x1F) |
1767 ((regp->sisRegs3D4[5] & 0x80) >> 2) |
1775 regp->sisRegs3D4[3] = (regp->sisRegs3D4[3] & ~0x1F) | (i & 0x1F);
1776 regp->sisRegs3D4[5] = (regp->sisRegs3D4[5] & ~0x80) | ((i << 2) & 0x80);
1784 SiS_VBlankKGA(DisplayModePtr mode, SISRegPtr regp, int nBits, unsigned int Flags)
1791 regp->sisRegs3D4[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
1794 int i = regp->sisRegs3D4[22] | ExtBits;
1799 (!(regp->sisRegs3D4[9] & 0x9F)) ) { /* 1 scanline/row */
1806 regp->sisRegs3D4[22] = i & 0xFF;
1816 SISRegPtr regp = &pSiS->ModeReg;
1822 regp->sisRegMiscOut = 0x23;
1823 if(mode->Flags & V_NHSYNC) regp->sisRegMiscOut |= 0x40;
1824 if(mode->Flags & V_NVSYNC) regp->sisRegMiscOut |= 0x80;
1831 if(VDisplay < 400) regp->sisRegMiscOut = 0xA3; /* +hsync -vsync */
1832 else if (VDisplay < 480) regp->sisRegMiscOut = 0x63; /* -hsync +vsync */
1833 else if (VDisplay < 768) regp->sisRegMiscOut = 0xE3; /* -hsync -vsync */
1834 else regp->sisRegMiscOut = 0x23; /* +hsync +vsync */
1837 regp->sisRegMiscOut |= (mode->ClockIndex & 0x03) << 2;
1840 if(depth == 4) regp->sisRegs3C4[0] = 0x02;
1841 else regp->sisRegs3C4[0] = 0x00;
1843 if(mode->Flags & V_CLKDIV2) regp->sisRegs3C4[1] = 0x09;
1844 else regp->sisRegs3C4[1] = 0x01;
1846 regp->sisRegs3C4[2] = 0x0F;
1848 regp->sisRegs3C4[3] = 0x00;
1850 if(depth < 8) regp->sisRegs3C4[4] = 0x06;
1851 else regp->sisRegs3C4[4] = 0x0E;
1854 regp->sisRegs3D4[0] = (mode->CrtcHTotal >> 3) - 5;
1855 regp->sisRegs3D4[1] = (mode->CrtcHDisplay >> 3) - 1;
1856 regp->sisRegs3D4[2] = (mode->CrtcHBlankStart >> 3) - 1;
1857 regp->sisRegs3D4[3] = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80;
1859 if(i < 0x80) regp->sisRegs3D4[3] |= i;
1860 regp->sisRegs3D4[4] = (mode->CrtcHSyncStart >> 3) - fixsync;
1861 regp->sisRegs3D4[5] = ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2) |
1863 regp->sisRegs3D4[6] = (mode->CrtcVTotal - 2) & 0xFF;
1864 regp->sisRegs3D4[7] = (((mode->CrtcVTotal - 2) & 0x100) >> 8) |
1872 regp->sisRegs3D4[8] = 0x00;
1873 regp->sisRegs3D4[9] = (((mode->CrtcVBlankStart - 1) & 0x200) >> 4) | 0x40;
1874 if(mode->Flags & V_DBLSCAN) regp->sisRegs3D4[9] |= 0x80;
1875 if(mode->VScan >= 32) regp->sisRegs3D4[9] |= 0x1F;
1876 else if (mode->VScan > 1) regp->sisRegs3D4[9] |= mode->VScan - 1;
1877 regp->sisRegs3D4[10] = 0x00;
1878 regp->sisRegs3D4[11] = 0x00;
1879 regp->sisRegs3D4[12] = 0x00;
1880 regp->sisRegs3D4[13] = 0x00;
1881 regp->sisRegs3D4[14] = 0x00;
1882 regp->sisRegs3D4[15] = 0x00;
1883 regp->sisRegs3D4[16] = (mode->CrtcVSyncStart - fixsync) & 0xFF;
1884 regp->sisRegs3D4[17] = ((mode->CrtcVSyncEnd - fixsync) & 0x0F) | 0x20;
1885 regp->sisRegs3D4[18] = (mode->CrtcVDisplay - 1) & 0xFF;
1886 regp->sisRegs3D4[19] = pScrn->displayWidth >> 4;
1887 regp->sisRegs3D4[20] = 0x00;
1888 regp->sisRegs3D4[21] = (mode->CrtcVBlankStart - 1) & 0xFF;
1889 regp->sisRegs3D4[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
1890 if(depth < 8) regp->sisRegs3D4[23] = 0xE3;
1891 else regp->sisRegs3D4[23] = 0xC3;
1892 regp->sisRegs3D4[24] = 0xFF;
1895 SiS_HBlankKGA(mode, regp, 0, SISKGA_FIX_OVERSCAN | SISKGA_ENABLE_ON_ZERO);
1897 SiS_VBlankKGA(mode, regp, 0, SISKGA_FIX_OVERSCAN | SISKGA_ENABLE_ON_ZERO);
1900 regp->sisRegsGR[0] = 0x00;
1901 regp->sisRegsGR[1] = 0x00;
1902 regp->sisRegsGR[2] = 0x00;
1903 regp->sisRegsGR[3] = 0x00;
1904 regp->sisRegsGR[4] = 0x00;
1905 if(depth == 4) regp->sisRegsGR[5] = 0x02;
1906 else regp->sisRegsGR[5] = 0x40;
1907 regp->sisRegsGR[6] = 0x05; /* only map 64k VGA memory !!!! */
1908 regp->sisRegsGR[7] = 0x0F;
1909 regp->sisRegsGR[8] = 0xFF;
1913 regp->sisRegsATTR[i] = i;
1915 if(depth == 4) regp->sisRegsATTR[16] = 0x81;
1916 else regp->sisRegsATTR[16] = 0x41;
1917 if(depth >= 4) regp->sisRegsATTR[17] = 0xFF;
1918 else regp->sisRegsATTR[17] = 0x01;
1919 regp->sisRegsATTR[18] = 0x0F;
1920 regp->sisRegsATTR[19] = 0x00;
1921 regp->sisRegsATTR[20] = 0x00;