Lines Matching refs:P3c4
175 USHORT P3c4, PVB_DEVICE_INFO pVBInfo);
177 USHORT P3c4, PVB_DEVICE_INFO pVBInfo);
179 USHORT P3c4, PVB_DEVICE_INFO pVBInfo);
281 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x05 , 0x86 ) ;
288 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ;
291 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ;
294 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; */
300 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ;
305 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ;
309 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
342 temp = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) ;
366 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x07, pVBInfo->SR07);
371 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
372 XGI_SetReg( (XGIIOADDRESS)pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
375 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x11, 0x0F);
376 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x1F, pVBInfo->SR1F);
377 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x20, 0x20); */
378 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
381 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
383 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
386 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x11 , SR11 ) ; */
395 temp1 = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3B ) ;
458 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x23, pVBInfo->SR23);
459 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x24, pVBInfo->SR24);
460 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
482 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x27 , 0x1F ) ;
487 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x31, (pVBInfo->SR31 & 0x3F) | 0x40);
488 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x32, (pVBInfo->SR32 & 0xFC) | 0x01);
491 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x31, pVBInfo->SR31);
492 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x32, pVBInfo->SR32);
494 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x33, pVBInfo->SR33);
499 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4);
560 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
570 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ;
571 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ;
572 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x20 , 0x20 ) ;
588 temp =( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) ;
596 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , pVBInfo->SR21 ) ;
599 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x22 , pVBInfo->SR22 ) ;
606 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x22, pVBInfo->SR22 & 0xFE);
609 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x22, pVBInfo->SR22);
612 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x21, pVBInfo->SR21);
743 tempal = (UCHAR)XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x06 ) ;
748 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ;
753 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ;
760 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ;
790 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) & 0x02 ;
793 data = ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
805 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x3B ) ;
866 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 ) ;
868 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
871 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
882 void XGINew_DDR1x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4,
885 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x01 ) ;
887 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ;
889 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ;
890 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
891 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
896 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ;
898 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ;
900 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ;
901 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
902 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
906 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
909 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x01 ) ; /*TSop DRAM DLL pin jump to A9*/
911 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ; /*TSop DRAM DLL pin jump to A9*/
913 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
914 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
916 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ;
918 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
919 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ;
920 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
921 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
922 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ;
932 void XGINew_DDR2x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4,
935 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ;
937 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ;
939 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ;
940 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
941 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
946 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ;
948 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ;
950 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ;
951 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
952 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
956 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
957 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */
958 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ; /*TSop DRAM DLL pin jump to A9*/
959 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
960 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
962 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ;
964 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */
965 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
966 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ;
967 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
968 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
969 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ;
979 void XGINew_DDR2_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4,
982 USHORT P3d4 = P3c4 + 0x10 ;
985 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x28 , 0x64 ) ; /* SR28 */
986 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x29 , 0x63 ) ; /* SR29 */
988 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ;
989 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ;
990 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
991 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
992 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0xC5 ) ;
993 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x23 ) ;
994 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
995 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
999 if( P3c4 != pVBInfo->P3c4 )
1001 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x28 ) ;
1002 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x28 , data ) ; /* SR28 */
1003 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x29 ) ;
1004 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x29 , data ) ; /* SR29 */
1005 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2A ) ;
1006 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2A , data ) ; /* SR2A */
1008 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2E ) ;
1009 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2e , data ) ; /* SR2E */
1010 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2F ) ;
1011 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2f , data ) ; /* SR2F */
1012 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x30 ) ;
1013 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x30 , data ) ; /* SR30 */
1019 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0xC5 ) ;
1020 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x23 ) ;
1021 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
1022 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
1024 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */
1026 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */
1028 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x72 ) ; */
1029 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
1030 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x06 ) ;
1031 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ;
1032 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ;
1042 void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo)
1044 USHORT P3d4 = P3c4 + 0x10 ;
1055 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS2*/
1056 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
1057 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
1059 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
1062 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS3*/
1063 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
1064 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
1066 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
1069 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS1*/
1070 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
1071 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
1073 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
1076 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ /*MRS, DLL Enable*/
1077 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
1078 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
1080 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
1081 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
1084 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
1086 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
1088 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ /*MRS, DLL Reset*/
1089 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
1090 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
1093 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
1096 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ /*MRS, ODT*/
1097 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
1098 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
1100 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
1103 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS*/
1104 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
1105 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
1107 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
1110 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
1119 void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo)
1121 USHORT P3d4 = P3c4 + 0x10 ;
1130 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
1131 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ;
1132 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ;
1133 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ;
1135 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
1136 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ;
1137 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ;
1138 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ;
1140 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
1141 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ;
1142 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ;
1143 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ;
1145 /* XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ;*/ /* MRS1 */
1146 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
1147 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ;
1148 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ;
1149 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ;
1152 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */
1154 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */
1157 /*XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ;*/ /* MRS2 */
1158 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
1159 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ;
1160 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ;
1161 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ;
1172 void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo)
1174 USHORT P3d4 = P3c4 + 0x10 ;
1182 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
1183 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ;
1185 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x10 ) ;
1187 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x90 ) ;
1189 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
1190 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ;
1192 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
1194 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
1197 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
1198 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ;
1200 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
1202 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
1204 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
1205 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x06 ) ; /*[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM*/
1207 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
1209 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
1212 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */
1214 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */
1217 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
1218 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x04 ) ; /* DLL without Reset for XG27 Hynix DRAM*/
1220 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
1222 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
1224 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x80 ); /*XG27 OCD ON */
1225 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x46 );
1227 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
1229 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
1231 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 );
1232 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 );
1234 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
1236 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
1239 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */
1241 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; /* SR1B */
1255 P3c4 = Port - 0x10 ;
1269 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
1303 XGINew_DDR1x_MRS_340( HwDeviceExtension , P3c4 , pVBInfo ) ;
1318 P3c4 = Port - 0x10 ;
1360 XGINew_DDR2x_MRS_340( HwDeviceExtension , P3c4 , pVBInfo ) ;
1374 P3c4 = Port - 0x10 ;
1396 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1398 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1400 XGINew_DDR2_MRS_340( HwDeviceExtension , P3c4, pVBInfo ) ;
1416 P3c4 = Port - 0x10 ;
1528 /*XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0xC0 ) ;*/ /* SR17 DDRII */
1529 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1531 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1535 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1537 XGI_SetReg((XGIIOADDRESS) P3c4, 0x1A, 0x87); /* SR1A */
1547 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1562 P3c4 = Port - 0x10 ;
1666 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1667 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1686 /* data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 ) ; */
1689 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ;
1691 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ;
1693 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ;
1695 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ;
1697 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ;
1699 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ;
1701 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ;
1703 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ;
1708 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data);
1716 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data);
1721 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data);
1728 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data);
1748 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ;
1749 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1753 /* data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1 ) ;
1755 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x01 , data ) ; */ /* Turn OFF Display */
1759 data=XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ;
1760 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1778 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ;
1779 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /*disable read cache*/
1781 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1 ) ;
1783 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x01 , data ) ; /*Turn OFF Display*/
1787 data=XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ;
1788 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /*enable read cache*/
1807 XGINew_DDR1x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ;
1812 data = ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1814 XGINew_DDR2x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ;
1816 XGINew_DDR1x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ;
1819 XGINew_DDR2_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1822 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1837 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B ) ;
1839 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , data ) ;
1853 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1871 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 ) ;
1891 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , data ) ;
1907 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1940 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ;
1978 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ;
2119 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) ;
2122 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ;
2123 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 ) ;
2125 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , data ) ;
2230 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 ) ;
2253 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2257 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; */
2278 data = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x13 ) ;
2301 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , ( XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2306 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2416 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) ;
2451 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2452 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2461 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2462 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2474 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2475 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2481 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2492 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ;
2493 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2502 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2503 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x31 ) ;
2515 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ;
2516 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2522 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2531 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2539 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2540 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2546 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2551 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2557 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2558 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2563 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2568 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2574 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2575 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2581 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2586 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2592 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2593 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2599 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2604 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2621 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2622 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2627 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2628 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2633 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2634 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2640 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2641 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2648 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2649 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2655 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2656 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2666 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2667 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2673 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2674 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x58 ) ;
2680 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2681 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x54 ) ;
2689 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2690 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x50+i ) ;
2697 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2698 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x58 ) ;
2704 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2705 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x54 ) ;
2713 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2714 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x50+i ) ;
2727 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2728 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2734 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2739 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2740 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2747 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2754 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2755 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2761 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2762 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2781 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2782 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2835 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2836 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2899 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2900 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2901 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2905 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2906 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2907 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2917 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ;
2972 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3396 void XGINew_DDR1x_MRS_XG20( USHORT P3c4 , PVB_DEVICE_INFO pVBInfo)
3399 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x01 ) ;
3400 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ;
3401 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
3402 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
3405 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ;
3406 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ;
3407 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ;
3408 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ;
3410 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3411 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */
3412 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x01 ) ;
3413 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x03 ) ;
3414 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ;
3416 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ;
3418 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */
3419 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3420 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ;
3421 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x03 ) ;
3422 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ;
3423 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ;
3442 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3444 XGINew_DDR2x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ;
3446 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3461 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3488 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3490 /*XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;*/
3491 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
3493 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;*/
3494 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */