110 src->cat6.type 1 1 xxxxxxxxx 00 00000 LoaD Global {SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}{OFF}], {SIZE} 0 src->srcs[1]->iim_val src->srcs[2]->uim_val LoaD Global {SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}+({SRC2}{OFF})<<{SRC2_BYTE_SHIFT}], {SIZE} {SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}+{SRC2}<<{SRC2_BYTE_SHIFT}{OFF}<<2], {SIZE} {SRC2_ADD_DWORD_SHIFT} > 0 0 1 {SRC2_ADD_DWORD_SHIFT} + 2 src->srcs[1] src->srcs[2]->uim_val src->srcs[3]->uim_val src->srcs[4]->uim_val x xxxxxxxx 1x x 00011 1 STore Global {SY}{JP}{NAME}.{TYPE} g[{SRC1}{OFF}], {SRC3}, {SIZE} ({OFF_HI} << 8) | {OFF_LO} 0 src->srcs[1]->iim_val src->srcs[1]->iim_val >> 8 src->srcs[2] src->srcs[3]->uim_val STore Global {SY}{JP}{NAME}.{TYPE} g[{SRC1}+({SRC2}{OFF})<<{DST_BYTE_SHIFT}], {SRC3}, {SIZE} {SY}{JP}{NAME}.{TYPE} g[{SRC1}+{SRC2}<<{DST_BYTE_SHIFT}{OFF}<<2], {SRC3}, {SIZE} {SRC2_ADD_DWORD_SHIFT} > 0 {SRC2_ADD_DWORD_SHIFT} + 2 0 1 src->srcs[1] src->srcs[2]->uim_val src->srcs[3]->uim_val src->srcs[4] src->srcs[5]->uim_val 1 x 1 xxxxxxxxx xx src->srcs[1]->uim_val src->srcs[0] src->srcs[2]->uim_val LoaD Local {SY}{JP}{NAME}.{TYPE} {DST}, l[{SRC}{OFF}], {SIZE} 00001 LoaD Private {SY}{JP}{NAME}.{TYPE} {DST}, p[{SRC}{OFF}], {SIZE} 00010 LoaD Local (variant used for passing data between geom stages) {SY}{JP}{NAME}.{TYPE} {DST}, l[{SRC}{OFF}], {SIZE} 01010 LoaD Local Varying - read directly from varying storage {SY}{JP}{NAME}.{TYPE} {DST}, l[{OFF}], {SIZE} 0 xxxxxxxx 11 xxxxxxxxx xx 11111 src->srcs[1]->uim_val src->srcs[0]->uim_val ({OFF_HI} << 8) | {OFF_LO} xxxxxxxxx 1 1 xx src->cat6.dst_offset >> 8 src->cat6.dst_offset & 0xff src->srcs[1] src->srcs[0]" src->srcs[2]->uim_val STore Local {SY}{JP}{NAME}.{TYPE} l[{DST}{OFF}], {SRC}, {SIZE} x 00100 STore Private {SY}{JP}{NAME}.{TYPE} p[{DST}{OFF}], {SRC}, {SIZE} 0 00101 STore Local (variant used for passing data between geom stages) {SY}{JP}{NAME}.{TYPE} l[{DST}{OFF}], {SRC}, {SIZE} x 01011 STore Const - used for shader prolog (between shps and shpe) to store "uniform folded" values into CONST file NOTE: TYPE field actually seems to be set to different values (ie f32 vs u32), but I *think* it does not matter. (There is SP_MODE_CONTROL.CONSTANT_DEMOTION_ENABLE, but I think float results are already converted to 32b) NOTE: this could be the "old" encoding, although it would conflict with stgb from earlier gens {SY}{JP}{NAME} c[{DST}], {SRC}, {SIZE} x xxxxxxxxxxxxxx 1 xxxxx xxxxxxxxx xx 11100 src->srcs[0]->uim_val src->srcs[1] {SY}{JP}{NAME}.{TYPE}.{D}d {DST}, g[{SSBO}] x xxxxxxxx x xx xxxxxxxx x x xxxxxxxx 0 x 01111 src->cat6.d - 1 src->srcs[0] !!(src->srcs[0]->flags & IR3_REG_IMMED) x src->cat6.d - 1 src src->cat6.iim_val - 1 src->srcs[0] !!(src->srcs[0]->flags & IR3_REG_IMMED) {SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE} {DST}, g[{SSBO}], {SRC1}, {SRC2} xxxxxxxx x src->srcs[1] !!(src->srcs[1]->flags & IR3_REG_IMMED) src->srcs[2] !!(src->srcs[2]->flags & IR3_REG_IMMED) 11011 x 00110 1 {SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE} g[{SSBO}], {SRC1}, {SRC2}, {SRC3} 1 xxxxxxxxx src->srcs[1] !!(src->srcs[1]->flags & IR3_REG_IMMED) src->srcs[2] !!(src->srcs[2]->flags & IR3_REG_IMMED) src->srcs[3] !!(src->srcs[3]->flags & IR3_REG_IMMED) 11100 11101 Base for atomic instructions (I think mostly a4xx+, as a3xx didn't have real image/ssbo.. it was all just global). Still used as of a6xx for local. NOTE that existing disasm and asm parser expect atomic inc/dec to still have an extra src. For now, match that. {SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.g {DST}, g[{SSBO}], {SRC1}, {SRC2}, {SRC3} {SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.l {DST}, l[{SRC1}], {SRC2} 1 xxxxxxxx x 00000000 0 !!(src->flags & IR3_INSTR_G) src src->cat6.d - 1 src->cat6.iim_val - 1 src->srcs[0] !!(src->srcs[0]->flags & IR3_REG_IMMED) extract_cat6_SRC(src, 0) !!(extract_cat6_SRC(src, 0)->flags & IR3_REG_IMMED) extract_cat6_SRC(src, 1) !!(extract_cat6_SRC(src, 1)->flags & IR3_REG_IMMED) extract_cat6_SRC(src, 2) !!(extract_cat6_SRC(src, 2)->flags & IR3_REG_IMMED) 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 Base for new instruction encoding that started being used with a6xx for instructions supporting bindless mode. 00 0 00000 extract_cat6_DESC_MODE(src) src->cat6.iim_val - 1 !!(src->flags & IR3_INSTR_B) src LoaD Constant - UBO load {K} {SY}{JP}{NAME}.{TYPE_SIZE}.k.{MODE}{BASE} c[a1.x], {SRC1}, {SRC2} {SY}{JP}{NAME}.offset{OFFSET}.{TYPE_SIZE}.{MODE}{BASE} {DST}, {SRC1}, {SRC2} x x 011110 1xx x11 1 0 !!(src->srcs[1]->flags & IR3_REG_IMMED) src->cat6.d src->srcs[1] src->srcs[0] GET Shader Processor ID? {SY}{JP}{NAME}.{TYPE} {DST} 0 xx x 100100 x1xx xxxxxxxx xxxxxxxx 1x GET Wavefront ID {SY}{JP}{NAME}.{TYPE} {DST} 0 xx x 100101 x1xx xxxxxxxx xxxxxxxx 1x RESourceINFO - returns image/ssbo dimensions (3 components) {SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.{MODE}{BASE} {DST}, {SSBO} 0 001111 0110 xxxxxxxx 1x src->cat6.d - 1 src src->srcs[0] src->srcs[1] IBO (ie. Image/SSBO) instructions {SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.{MODE}{BASE} {SRC1}, {SRC2}, {SSBO} 0110 src src->cat6.d - 1 src->srcs[0] src->srcs[2] src->srcs[1] STore IBo 0 011101 10 LoaD IBo x 000110 10 src->dsts[0] x 010000 11 x 010001 11 x 010010 11 x 010101 11 x 010110 11 x 010111 11 x 011000 11 x 011001 11 x 011010 11 {D_MINUS_ONE} + 1 {TYPE_SIZE_MINUS_ONE} + 1 {G} {TYPED} typed untyped src->cat6.typed {BINDLESS} .base{BASE} src->cat6.base Source value that can be either immed or gpr {SRC_IM} {IMMED} r{GPR}.{SWIZ} src->num >> 2 src->num & 0x3 src->iim_val {MODE} == 0 Source mode for "new" a6xx+ instruction encodings Immediate index. Index from a uniform register (ie. does not depend on flow control) Index from a non-uniform register (ie. potentially depends on flow control)