| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| H A D | common_baco.h | 40 uint32_t reg_offset; member in struct:baco_cmd_entry
52 uint32_t reg_offset; member in struct:soc15_baco_cmd_entry
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | soc15.h | 51 uint32_t reg_offset; member in struct:soc15_reg_entry
61 uint32_t reg_offset; member in struct:soc15_allowed_register_entry
70 uint32_t reg_offset; member in struct:soc15_ras_field_entry
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| H A D | mmsch_v1_0.h | 65 uint32_t reg_offset : 28; member in struct:mmsch_v1_0_cmd_direct_reg_header
70 uint32_t reg_offset : 20; member in struct:mmsch_v1_0_cmd_indirect_reg_header
101 mmsch_v1_0_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write * direct_wt,uint32_t * init_table,uint32_t reg_offset,uint32_t value) argument
111 mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write * direct_rd_mod_wt,uint32_t * init_table,uint32_t reg_offset,uint32_t mask,uint32_t data) argument
123 mmsch_v1_0_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling * direct_poll,uint32_t * init_table,uint32_t reg_offset,uint32_t mask,uint32_t wait) argument
[all...] |
| H A D | amdgpu_jpeg_v1_0.c | 41 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) argument
60 uint32_t reg, reg_offset, val, mask, i; local in function:jpeg_v1_0_decode_ring_set_patch_ring
350 uint32_t reg_offset = (reg << 2); local in function:jpeg_v1_0_decode_ring_emit_reg_wait
394 uint32_t reg_offset = (reg << 2); local in function:jpeg_v1_0_decode_ring_emit_wreg
[all...] |
| H A D | amdgpu_jpeg_v2_0.c | 605 uint32_t reg_offset = (reg << 2); local in function:jpeg_v2_0_dec_ring_emit_reg_wait
646 uint32_t reg_offset = (reg << 2); local in function:jpeg_v2_0_dec_ring_emit_wreg
[all...] |
| H A D | amdgpu_amdkfd_gfx_v10.c | 772 kgd_address_watch_get_offset(struct kgd_dev * kgd,unsigned int watch_point_id,unsigned int reg_offset) argument
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| H A D | amdgpu_amdkfd_gfx_v8.c | 635 kgd_address_watch_get_offset(struct kgd_dev * kgd,unsigned int watch_point_id,unsigned int reg_offset) argument
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| H A D | amdgpu_amdkfd_gfx_v9.c | 702 kgd_gfx_v9_address_watch_get_offset(struct kgd_dev * kgd,unsigned int watch_point_id,unsigned int reg_offset) argument
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| H A D | amdgpu_nv.c | 215 nv_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset) argument
232 nv_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset) argument
245 nv_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value) argument
[all...] |
| H A D | amdgpu_vi.c | 558 vi_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset) argument
654 vi_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value) argument
[all...] |
| H A D | amdgpu_amdkfd_gfx_v7.c | 662 kgd_address_watch_get_offset(struct kgd_dev * kgd,unsigned int watch_point_id,unsigned int reg_offset) argument
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| H A D | amdgpu_cik.c | 1053 cik_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset) argument
1149 cik_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value) argument
[all...] |
| H A D | amdgpu_sdma_v5_0.c | 1399 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? local in function:sdma_v5_0_set_trap_irq_state
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| H A D | amdgpu_si.c | 1035 si_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset) argument
1110 si_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value) argument
[all...] |
| H A D | amdgpu_soc15.c | 363 soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset) argument
380 soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset) argument
395 soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value) argument
[all...] |
| H A D | amdgpu_gfx_v6_0.c | 405 u32 reg_offset, split_equal_to_row_size, *tilemode; local in function:gfx_v6_0_tiling_mode_table_init
[all...] |
| /src/sys/dev/isa/ |
| H A D | nca_isa.c | 123 nca_isa_test(bus_space_tag_t iot, bus_space_handle_t ioh, bus_size_t reg_offset) argument
179 bus_size_t base_offset, reg_offset = 0; local in function:nca_isa_find
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_ni_dma.c | 197 u32 reg_offset, wb_offset; local in function:cayman_dma_resume
[all...] |
| H A D | radeon_cik_sdma.c | 257 u32 rb_cntl, reg_offset; local in function:cik_sdma_gfx_stop
311 uint32_t reg_offset, value; local in function:cik_sdma_ctx_switch_enable
338 u32 me_cntl, reg_offset; local in function:cik_sdma_enable
375 u32 reg_offset, wb_offset; local in function:cik_sdma_gfx_resume
[all...] |
| H A D | radeon_rv770_dpm.c | 250 rv770_write_smc_soft_register(struct radeon_device * rdev,u16 reg_offset,u32 value) argument
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| /src/usr.bin/scmdctl/ |
| H A D | common.c | 221 uint8_t reg, reg_index = 0, reg_offset = 0; local in function:common_invert_motor
263 uint8_t reg, reg_index = 0, reg_offset = 0; local in function:common_bridge_motor
[all...] |
| /src/sys/arch/mac68k/obio/ |
| H A D | esp.c | 183 unsigned long reg_offset; local in function:espattach
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| H A D | intel_dsi_vbt.c | 460 u8 reg_offset = *(data + 5); local in function:mipi_exec_i2c
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| H A D | kfd_pm4_headers_diq.h | 192 unsigned int reg_offset:16; member in struct:pm4__set_config_reg::__anon2b5eba7e130a::__anon2b5eba7e1408
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| /src/sys/arch/macppc/dev/ |
| H A D | platinumfb.c | 306 platinumfb_read_cmap_reg(struct platinumfb_softc *sc, int reg_offset) argument
299 platinumfb_write_cmap_reg(struct platinumfb_softc * sc,int reg_offset,uint8_t val) argument
|