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    Searched defs:OffsetReg (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallLowering.cpp 103 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
Thumb2SizeReduction.cpp 567 unsigned OffsetReg = 0;
571 OffsetReg = MI->getOperand(2).getReg();
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFrameLowering.cpp 248 Register OffsetReg = MRI.createVirtualRegister(PtrRC);
249 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg)
253 .addReg(OffsetReg);
300 Register OffsetReg = MRI.createVirtualRegister(PtrRC);
301 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg)
309 .addReg(OffsetReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallLowering.cpp 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64CallLowering.cpp 255 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
257 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 269 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
271 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
MipsSEInstrInfo.cpp 887 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
895 Register OffsetReg = I->getOperand(0).getReg();
909 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
MipsISelLowering.cpp 2545 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2547 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2550 DAG.getRegister(OffsetReg, Ty),
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 203 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset);
205 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
408 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset);
410 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
SIRegisterInfo.cpp 694 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
700 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
707 .addReg(OffsetReg, RegState::Kill)
713 .addReg(OffsetReg, RegState::Kill)
AMDGPURegisterBankInfo.cpp 1558 Register OffsetReg = MI.getOperand(3).getReg();
1568 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/
LanaiAsmParser.cpp 132 unsigned OffsetReg;
178 return Mem.OffsetReg;
618 Op->Mem.OffsetReg = 0;
626 unsigned OffsetReg = Op->getReg();
630 Op->Mem.OffsetReg = OffsetReg;
642 Op->Mem.OffsetReg = 0;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 248 unsigned OffsetReg;
339 return Mem.OffsetReg;
525 unsigned offsetReg = Op->getReg();
528 Op->Mem.OffsetReg = offsetReg;
537 Op->Mem.OffsetReg = Sparc::G0; // always 0
549 Op->Mem.OffsetReg = 0;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 94 unsigned OffsetReg = 0;
120 OffsetReg = Reg;
124 return OffsetReg;

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