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    Searched defs:PredR (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenMux.cpp 92 unsigned PredR = 0;
108 unsigned DefR, PredR;
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
256 if (F != CM.end() && F->second.PredR != PR) {
263 F->second.PredR = PR;
344 .addReg(MX.PredR)
HexagonEarlyIfConv.cpp 125 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {}
131 unsigned PredR = 0;
146 << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
197 MachineInstr *MI, unsigned PredR, bool IfTrue);
200 unsigned PredR, bool IfTrue);
203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
253 Register PredR = T1I->getOperand(0).getReg();
271 // Record the true/false blocks in such a way that "true" means "if (PredR)",
272 // and "false" means "if (!PredR)"
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HexagonExpandCondsets.cpp 223 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
230 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
744 /// under the conditions given by PredR and Cond, and this function will ignore
747 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
760 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
764 // Check the defs. If the PredR is defined, invalidate it. If RD is
770 if (RR.Reg == PredR) {
854 /// PredR and Cond) at the point indicated by Where.
910 unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
919 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))
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HexagonHardwareLoops.cpp 462 unsigned PredR, PredPos, PredRegFlags;
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
466 MachineInstr *PredI = MRI->getVRegDef(PredR);
1337 Register PredR = CmpI->getOperand(0).getReg();
1345 if (MO.getReg() == PredR) // Found an intervening use of PredR.
1913 Register PredR = PN->getOperand(i).getReg();
1919 MachineOperand MO = MachineOperand::CreateReg(PredR, false);
HexagonISelLowering.cpp 375 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
376 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
382 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
EarlyCSE.cpp 416 CmpInst::Predicate PredL, PredR;
419 match(CondR, m_Cmp(PredR, m_Specific(X), m_Specific(Y))) &&
420 CmpInst::getInversePredicate(PredL) == PredR)
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineAndOrXor.cpp 264 /// and PredR are their predicates, respectively.
271 ICmpInst::Predicate &PredR) {
312 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) {
347 if (!ICmpInst::isEquality(PredR))
389 unsigned RightType = getMaskedICmpType(A, D, E, PredR);
399 Value *D, Value *E, ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
422 if (PredR != NewCC)
520 Value *D, Value *E, ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
522 assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
536 PredL, PredR, Builder))
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