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    Searched defs:PrefAlign (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/IR/
DataLayout.cpp 110 retval.PrefAlign = pref_align;
119 && PrefAlign == rhs.PrefAlign
128 Align PrefAlign, uint32_t TypeByteWidth,
130 assert(ABIAlign <= PrefAlign && "Preferred alignment worse than ABI!");
134 retval.PrefAlign = PrefAlign;
144 && PrefAlign == rhs.PrefAlign
195 E.PrefAlign, E.TypeBitWidth)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
DataLayout.h 77 Align PrefAlign;
93 Align PrefAlign;
100 Align PrefAlign, uint32_t TypeByteWidth,
181 Error setPointerAlignment(uint32_t AddrSpace, Align ABIAlign, Align PrefAlign,
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGCall.cpp 1127 auto PrefAlign = CGF.CGM.getDataLayout().getPrefTypeAlignment(Ty);
1128 CharUnits Align = std::max(MinAlign, CharUnits::fromQuantity(PrefAlign));
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
DeadStoreElimination.cpp 573 Align PrefAlign = EarlierIntrinsic->getDestAlign().valueOrOne();
587 // PrefAlign = std::min(DL.getPrefTypeAlign(LargestType), PrefAlign);
591 // Compute start and size of the region to remove. Make sure 'PrefAlign' is
597 offsetToAlignment(uint64_t(LaterStart - EarlierStart), PrefAlign);
609 uint64_t Off = offsetToAlignment(ToRemoveSize, PrefAlign);
611 if (ToRemoveSize <= (PrefAlign.value() - Off))
613 ToRemoveSize -= PrefAlign.value() - Off;
615 assert(isAligned(PrefAlign, ToRemoveSize) &&
640 EarlierIntrinsic->setDestAlignment(PrefAlign);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 2306 Align PrefAlign =
2308 if (Alignment < PrefAlign) {
4787 Align PrefAlign = TD.getPrefTypeAlign(ResVT.getTypeForEVT(*DAG.getContext()));
4788 if (Alignment < PrefAlign) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CodeGenPrepare.cpp 2105 unsigned MinSize, PrefAlign;
2106 if (TLI->shouldAlignPointerArgs(CI, MinSize, PrefAlign)) {
2119 if ((Offset2 & (PrefAlign-1)) != 0)
2122 if ((AI = dyn_cast<AllocaInst>(Val)) && AI->getAlignment() < PrefAlign &&
2124 AI->setAlignment(Align(PrefAlign));
2131 GV->getPointerAlignment(*DL) < PrefAlign &&
2134 GV->setAlignment(MaybeAlign(PrefAlign));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 11906 const Align PrefAlign = TargetLowering::getPrefLoopAlignment(ML);
11913 return PrefAlign;
11927 if (Header->getAlignment() != PrefAlign)
11940 return PrefAlign;
11945 return PrefAlign;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1849 unsigned &PrefAlign) const {
1855 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
3613 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3617 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||

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