| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/ |
| H A D | radv_amdgpu_cs.c | 960 radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs) argument
1149 radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radv_winsys_sem_info * sem_info,bool can_patch) argument
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/ |
| H A D | radv_amdgpu_cs.c | 817 radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
907 radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
994 radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
1195 radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * bo_list,bool can_patch,struct radeon_winsys_fence * _fence) argument
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_device.c | 2448 radv_get_preamble_cs(struct radv_queue * queue,uint32_t scratch_size,uint32_t compute_scratch_size,uint32_t esgs_ring_size,uint32_t gsvs_ring_size,bool needs_tess_rings,bool needs_sample_positions,struct radeon_cmdbuf ** initial_full_flush_preamble_cs,struct radeon_cmdbuf ** initial_preamble_cs,struct radeon_cmdbuf ** continue_preamble_cs) argument
[all...] |
| H A D | radv_private.h | 661 struct radeon_cmdbuf *continue_preamble_cs; member in struct:radv_queue
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| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_device.c | 3743 radv_get_preamble_cs(struct radv_queue * queue,uint32_t scratch_size_per_wave,uint32_t scratch_waves,uint32_t compute_scratch_size_per_wave,uint32_t compute_scratch_waves,uint32_t esgs_ring_size,uint32_t gsvs_ring_size,bool needs_tess_rings,bool needs_gds,bool needs_gds_oa,bool needs_sample_positions,struct radeon_cmdbuf ** initial_full_flush_preamble_cs,struct radeon_cmdbuf ** initial_preamble_cs,struct radeon_cmdbuf ** continue_preamble_cs) argument
4392 radv_get_preambles(struct radv_queue * queue,const VkCommandBuffer * cmd_buffers,uint32_t cmd_buffer_count,struct radeon_cmdbuf ** initial_full_flush_preamble_cs,struct radeon_cmdbuf ** initial_preamble_cs,struct radeon_cmdbuf ** continue_preamble_cs) argument
4694 struct radeon_cmdbuf *continue_preamble_cs = NULL; local in function:radv_queue_submit_deferred
[all...] |
| H A D | radv_private.h | 690 struct radeon_cmdbuf *continue_preamble_cs; member in struct:radv_queue
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