| /xsrc/external/mit/MesaLib/dist/src/intel/common/ |
| H A D | intel_disasm.c | 48 const brw_inst *insn = assembly + offset; local in function:intel_disasm_find_end
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| /xsrc/external/mit/MesaLib.old/dist/src/intel/common/ |
| H A D | gen_disasm.c | 53 const brw_inst *insn = assembly + offset; local in function:gen_disasm_find_end
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_sched_gm107.h | 132 LiveBarUse(Instruction *insn, Instruction *usei) argument
134 Instruction *insn; member in struct:nv50_ir::SchedDataCalculatorGM107::LiveBarUse
139 LiveBarDef(Instruction *insn, Instruction *defi) argument
141 Instruction *insn; member in struct:nv50_ir::SchedDataCalculatorGM107::LiveBarDef
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| H A D | nv50_ir_lowering_helper.cpp | 30 LoweringHelper::visit(Instruction *insn) argument
59 handleABS(Instruction * insn) argument
83 handleCVT(Instruction * insn) argument
113 handleMAXMIN(Instruction * insn) argument
149 handleMOV(Instruction * insn) argument
177 handleNEG(Instruction * insn) argument
191 handleSAT(Instruction * insn) argument
208 handleSLCT(CmpInstruction * insn) argument
242 handleLogOp(Instruction * insn) argument
[all...] |
| H A D | nv50_ir_lowering_nvc0.h | 96 Instruction *insn; member in struct:nv50_ir::NVC0LegalizePostRA::TexUse
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| H A D | nv50_ir_bb.cpp | 239 BasicBlock::remove(Instruction *insn) argument
299 splitCommon(Instruction * insn,BasicBlock * bb,bool attach) argument
330 splitBefore(Instruction * insn,bool attach) argument
343 splitAfter(Instruction * insn,bool attach) argument
425 for (Instruction *insn = bb->getFirst(); insn; insn = insn->next) local in function:nv50_ir::Function::orderInstructions
485 Instruction *insn, *next; local in function:nv50_ir::Pass::doRun
[all...] |
| H A D | nv50_ir_emit_gv100.h | 38 const Instruction *insn; member in class:nv50_ir::CodeEmitterGV100
[all...] |
| H A D | nv50_ir_lowering_gm107.cpp | 224 GM107LoweringPass::handleDFDX(Instruction *insn) argument
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| H A D | nv50_ir_target_nv50.cpp | 469 TargetNV50::isModSupported(const Instruction *insn, int s, Modifier mod) const argument
505 TargetNV50::mayPredicate(const Instruction *insn, const Value *pred) const argument
[all...] |
| H A D | nv50_ir_target_nvc0.cpp | 444 TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const argument
484 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const argument
531 mayPredicate(const Instruction * insn,const Value * pred) const argument
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_helper.cpp | 30 LoweringHelper::visit(Instruction *insn) argument
59 handleABS(Instruction * insn) argument
83 handleCVT(Instruction * insn) argument
113 handleMAXMIN(Instruction * insn) argument
149 handleMOV(Instruction * insn) argument
177 handleNEG(Instruction * insn) argument
191 handleSAT(Instruction * insn) argument
208 handleSLCT(CmpInstruction * insn) argument
242 handleLogOp(Instruction * insn) argument
[all...] |
| H A D | nv50_ir_lowering_nvc0.h | 94 Instruction *insn; member in struct:nv50_ir::NVC0LegalizePostRA::TexUse
|
| H A D | nv50_ir_bb.cpp | 239 BasicBlock::remove(Instruction *insn) argument
299 splitCommon(Instruction * insn,BasicBlock * bb,bool attach) argument
330 splitBefore(Instruction * insn,bool attach) argument
343 splitAfter(Instruction * insn,bool attach) argument
425 for (Instruction *insn = bb->getFirst(); insn; insn = insn->next) local in function:nv50_ir::Function::orderInstructions
485 Instruction *insn, *next; local in function:nv50_ir::Pass::doRun
[all...] |
| H A D | nv50_ir_build_util.h | 261 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkOp
|
| H A D | nv50_ir_lowering_gm107.cpp | 205 GM107LoweringPass::handleDFDX(Instruction *insn) argument
|
| H A D | nv50_ir_print.cpp | 814 PrintPass::visit(Instruction *insn) argument
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| H A D | nv50_ir_target_nv50.cpp | 458 TargetNV50::isModSupported(const Instruction *insn, int s, Modifier mod) const argument
494 TargetNV50::mayPredicate(const Instruction *insn, const Value *pred) const argument
[all...] |
| H A D | nv50_ir_target_nvc0.cpp | 434 TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const argument
474 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const argument
521 mayPredicate(const Instruction * insn,const Value * pred) const argument
[all...] |
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/ |
| H A D | brw_wm.c | 170 struct brw_instruction *insn; local in function:brw_fb_write
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/ |
| H A D | brw_wm.c | 170 struct brw_instruction *insn; local in function:brw_fb_write
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| H A D | brw_inst.h | 356 brw_inst_3src_a1_src2_imm(MAYBE_UNUSED const struct gen_device_info * devinfo,const brw_inst * insn) argument
364 brw_inst_set_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info * devinfo,brw_inst * insn,uint16_t value) argument
372 brw_inst_set_3src_a1_src2_imm(MAYBE_UNUSED const struct gen_device_info * devinfo,brw_inst * insn,uint16_t value) argument
810 brw_inst_imm_ud(const struct gen_device_info * devinfo,const brw_inst * insn) argument
817 brw_inst_imm_uq(MAYBE_UNUSED const struct gen_device_info * devinfo,const brw_inst * insn) argument
825 brw_inst_imm_f(const struct gen_device_info * devinfo,const brw_inst * insn) argument
837 brw_inst_imm_df(const struct gen_device_info * devinfo,const brw_inst * insn) argument
849 brw_inst_set_imm_d(const struct gen_device_info * devinfo,brw_inst * insn,int value) argument
857 brw_inst_set_imm_ud(const struct gen_device_info * devinfo,brw_inst * insn,unsigned value) argument
865 brw_inst_set_imm_f(const struct gen_device_info * devinfo,brw_inst * insn,float value) argument
878 brw_inst_set_imm_df(const struct gen_device_info * devinfo,brw_inst * insn,double value) argument
891 brw_inst_set_imm_uq(const struct gen_device_info * devinfo,brw_inst * insn,uint64_t value) argument
[all...] |
| H A D | brw_eu.c | 359 const brw_inst *insn = assembly + offset; local in function:brw_disassemble
|
| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| H A D | brw_inst.h | 492 brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info * devinfo,const brw_inst * insn) argument
503 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info * devinfo,brw_inst * insn,uint16_t value) argument
514 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info * devinfo,brw_inst * insn,uint16_t value) argument
1063 brw_inst_imm_ud(const struct intel_device_info * devinfo,const brw_inst * insn) argument
1070 brw_inst_imm_uq(ASSERTED const struct intel_device_info * devinfo,const brw_inst * insn) argument
1078 brw_inst_imm_f(const struct intel_device_info * devinfo,const brw_inst * insn) argument
1090 brw_inst_imm_df(const struct intel_device_info * devinfo,const brw_inst * insn) argument
1102 brw_inst_set_imm_d(const struct intel_device_info * devinfo,brw_inst * insn,int value) argument
1110 brw_inst_set_imm_ud(const struct intel_device_info * devinfo,brw_inst * insn,unsigned value) argument
1118 brw_inst_set_imm_f(const struct intel_device_info * devinfo,brw_inst * insn,float value) argument
1131 brw_inst_set_imm_df(const struct intel_device_info * devinfo,brw_inst * insn,double value) argument
1150 brw_inst_set_imm_uq(const struct intel_device_info * devinfo,brw_inst * insn,uint64_t value) argument
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/intel/tools/ |
| H A D | i965_asm.c | 343 const brw_inst *insn = store + offset; local in function:main
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv30/ |
| H A D | nv30_state.h | 116 uint32_t *insn; member in struct:nv30_fragprog
|