| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.h | 42 // CMOV
43 CMOV,
|
| ARCISelLowering.cpp | 144 case ARCISD::CMOV:
145 return "ARCISD::CMOV";
172 return DAG.getNode(ARCISD::CMOV, dl, TVal.getValueType(), TVal, FVal,
|
| /src/sys/external/mit/xen-include-public/dist/xen/include/public/arch-x86/ |
| cpufeatureset.h | 107 XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.h | 63 CMOV,
|
| M68kISelLowering.cpp | 2195 // M68k doesn't have an i8 cmov. If both operands are the result of a
2196 // truncate widen the cmov and push the truncate through. This avoids
2206 SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
2207 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
2211 // M68kISD::CMOV means set the result (which is operand 1) to the RHS if
2215 return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
2886 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
2887 // together with other CMOV pseudo-opcodes into a single basic-block with
2954 // This code lowers all pseudo-CMOV instructions. Generally it lowers thes
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 95 CMOV, // ARM conditional move instructions.
|
| ARMISelLowering.cpp | 1642 MAKE_CASE(ARMISD::CMOV)
4761 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4883 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4884 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4886 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4991 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4993 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4998 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR
[all...] |
| ARMISelDAGToDAG.cpp | 4016 case ARMISD::CMOV: {
4040 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 116 CMOV,
|
| X86ISelLowering.cpp | 448 // X86 wants to expand cmov itself.
5106 /// Is there a floating point cmov for the specific X86 condition code?
5107 /// Current x86 isa includes the following FP cmov instructions:
9210 // Perform the select in the scalar domain so we can use cmov.
22565 // Only perform this transform if CMOV is supported otherwise the select
22592 SDValue CMov = DAG.getNode(ISD::SELECT, DL, VT, Cmp, Add, N0);
22596 Created.push_back(CMov.getNode());
22600 DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i8));
23870 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
23871 // widen the cmov and push the truncate through. This avoids introducing a ne
[all...] |
| X86ISelDAGToDAG.cpp | 2981 case X86ISD::CMOV: CCOpNo = 2; break;
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| i386-gen.c | 118 "586|687|CMOV|FXSR" },
344 BITFIELD (CMOV),
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| i386-gen.c | 116 "586|687|CMOV|FXSR" },
328 BITFIELD (CMOV),
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| i386-gen.c | 116 "586|687|CMOV|FXSR" },
310 BITFIELD (CMOV),
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| i386-gen.c | 116 "586|687|CMOV|FXSR" },
328 BITFIELD (CMOV),
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-i386.c | 1109 SUBARCH (cmov, CMOV, CMOV, false),
5516 cfcmov<cc> %rM, %rN, %rN -> cmov<cc> %rM, %rN
5517 cfcmov<cc> %rM, %rN, %rM -> cmov<!cc> %rN, %rM
8053 if ((mnemonic + 4 == dot_p && !memcmp (mnemonic, "cmov", 4))
8064 && !memcmp (mnemonic, "cmov", 4)
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-i386.c | 1093 SUBARCH (cmov, CMOV, CMOV, false),
5354 cfcmov<cc> %rM, %rN, %rN -> cmov<cc> %rM, %rN
5355 cfcmov<cc> %rM, %rN, %rM -> cmov<!cc> %rN, %rM
7887 if ((mnemonic + 4 == dot_p && !memcmp (mnemonic, "cmov", 4))
7898 && !memcmp (mnemonic, "cmov", 4)
|
