1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Mips Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/MipsMCTargetDesc.h" 14 #include "Mips.h" 15 #include "TargetInfo/MipsTargetInfo.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; } 67 68 bool hasCOP3() const { 69 // Only present in MIPS-I and MIPS-II 70 return !hasMips32() && !hasMips3(); 71 } 72 73 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 74 ArrayRef<uint8_t> Bytes, uint64_t Address, 75 raw_ostream &CStream) const override; 76 }; 77 78 } // end anonymous namespace 79 80 // Forward declare these because the autogenerated code will reference them. 81 // Definitions are further down. 82 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 83 unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 87 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 98 unsigned RegNo, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 113 unsigned Insn, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 128 unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 133 unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 143 uint64_t Address, 144 const void *Decoder); 145 146 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 147 unsigned Insn, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 157 unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 192 unsigned RegNo, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 197 unsigned RegNo, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 202 unsigned RegNo, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 207 unsigned Offset, 208 uint64_t Address, 209 const void *Decoder); 210 211 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 212 unsigned Offset, 213 uint64_t Address, 214 const void *Decoder); 215 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 217 unsigned Insn, 218 uint64_t Address, 219 const void *Decoder); 220 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 222 unsigned Offset, 223 uint64_t Address, 224 const void *Decoder); 225 226 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 227 unsigned Offset, 228 uint64_t Address, 229 const void *Decoder); 230 231 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 232 unsigned Offset, 233 uint64_t Address, 234 const void *Decoder); 235 236 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 237 // shifted left by 1 bit. 238 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 239 unsigned Offset, 240 uint64_t Address, 241 const void *Decoder); 242 243 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 244 // shifted left by 1 bit. 245 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 246 unsigned Offset, 247 uint64_t Address, 248 const void *Decoder); 249 250 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 251 // shifted left by 1 bit. 252 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 253 unsigned Offset, 254 uint64_t Address, 255 const void *Decoder); 256 257 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 258 // shifted left by 1 bit. 259 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 260 unsigned Offset, 261 uint64_t Address, 262 const void *Decoder); 263 264 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 265 // shifted left by 1 bit. 266 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 267 unsigned Insn, 268 uint64_t Address, 269 const void *Decoder); 270 271 // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, 272 // which is shifted left by 2 bit. 273 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 274 unsigned Insn, 275 uint64_t Address, 276 const void *Decoder); 277 278 static DecodeStatus DecodeMem(MCInst &Inst, 279 unsigned Insn, 280 uint64_t Address, 281 const void *Decoder); 282 283 static DecodeStatus DecodeMemEVA(MCInst &Inst, 284 unsigned Insn, 285 uint64_t Address, 286 const void *Decoder); 287 288 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 289 unsigned Insn, 290 uint64_t Address, 291 const void *Decoder); 292 293 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 294 const void *Decoder); 295 296 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 297 unsigned Insn, 298 uint64_t Address, 299 const void *Decoder); 300 301 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 302 unsigned Insn, 303 uint64_t Address, 304 const void *Decoder); 305 306 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 307 unsigned Insn, 308 uint64_t Address, 309 const void *Decoder); 310 311 static DecodeStatus DecodeSyncI(MCInst &Inst, 312 unsigned Insn, 313 uint64_t Address, 314 const void *Decoder); 315 316 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, 317 unsigned Insn, 318 uint64_t Address, 319 const void *Decoder); 320 321 static DecodeStatus DecodeSynciR6(MCInst &Inst, 322 unsigned Insn, 323 uint64_t Address, 324 const void *Decoder); 325 326 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 327 uint64_t Address, const void *Decoder); 328 329 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 330 unsigned Insn, 331 uint64_t Address, 332 const void *Decoder); 333 334 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 335 unsigned Insn, 336 uint64_t Address, 337 const void *Decoder); 338 339 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 340 unsigned Insn, 341 uint64_t Address, 342 const void *Decoder); 343 344 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 345 unsigned Insn, 346 uint64_t Address, 347 const void *Decoder); 348 349 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 350 unsigned Insn, 351 uint64_t Address, 352 const void *Decoder); 353 354 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 355 unsigned Insn, 356 uint64_t Address, 357 const void *Decoder); 358 359 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 360 unsigned Insn, 361 uint64_t Address, 362 const void *Decoder); 363 364 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 365 uint64_t Address, 366 const void *Decoder); 367 368 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 369 uint64_t Address, 370 const void *Decoder); 371 372 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 376 const void *Decoder); 377 378 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 381 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 382 uint64_t Address, 383 const void *Decoder); 384 385 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 386 unsigned Insn, 387 uint64_t Address, 388 const void *Decoder); 389 390 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 391 unsigned Value, 392 uint64_t Address, 393 const void *Decoder); 394 395 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 396 unsigned Value, 397 uint64_t Address, 398 const void *Decoder); 399 400 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 401 unsigned Value, 402 uint64_t Address, 403 const void *Decoder); 404 405 template <unsigned Bits, int Offset, int Scale> 406 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 407 uint64_t Address, 408 const void *Decoder); 409 410 template <unsigned Bits, int Offset> 411 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 412 uint64_t Address, 413 const void *Decoder) { 414 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 415 Decoder); 416 } 417 418 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 419 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 420 uint64_t Address, 421 const void *Decoder); 422 423 static DecodeStatus DecodeInsSize(MCInst &Inst, 424 unsigned Insn, 425 uint64_t Address, 426 const void *Decoder); 427 428 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void *Decoder); 430 431 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 432 uint64_t Address, const void *Decoder); 433 434 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 435 uint64_t Address, const void *Decoder); 436 437 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 438 uint64_t Address, const void *Decoder); 439 440 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 441 uint64_t Address, const void *Decoder); 442 443 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 444 /// handle. 445 template <typename InsnType> 446 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 447 const void *Decoder); 448 449 template <typename InsnType> 450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 451 uint64_t Address, const void *Decoder); 452 453 template <typename InsnType> 454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 455 const void *Decoder); 456 457 template <typename InsnType> 458 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 459 uint64_t Address, const void *Decoder); 460 461 template <typename InsnType> 462 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 463 const void *Decoder); 464 465 template <typename InsnType> 466 static DecodeStatus 467 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 468 const void *Decoder); 469 470 template <typename InsnType> 471 static DecodeStatus 472 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 473 const void *Decoder); 474 475 template <typename InsnType> 476 static DecodeStatus 477 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 478 const void *Decoder); 479 480 template <typename InsnType> 481 static DecodeStatus 482 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 483 const void *Decoder); 484 485 template <typename InsnType> 486 static DecodeStatus 487 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 488 const void *Decoder); 489 490 template <typename InsnType> 491 static DecodeStatus 492 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 493 const void *Decoder); 494 495 template <typename InsnType> 496 static DecodeStatus 497 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 498 const void *Decoder); 499 500 template <typename InsnType> 501 static DecodeStatus 502 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 503 const void *Decoder); 504 505 template <typename InsnType> 506 static DecodeStatus 507 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 508 const void *Decoder); 509 510 template <typename InsnType> 511 static DecodeStatus 512 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 513 const void *Decoder); 514 515 template <typename InsnType> 516 static DecodeStatus 517 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 518 const void *Decoder); 519 520 template <typename InsnType> 521 static DecodeStatus 522 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 523 const void *Decoder); 524 525 template <typename InsnType> 526 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 527 const void *Decoder); 528 529 template <typename InsnType> 530 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 531 const void *Decoder); 532 533 template <typename InsnType> 534 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 535 const void *Decoder); 536 537 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 538 uint64_t Address, 539 const void *Decoder); 540 541 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 542 uint64_t Address, 543 const void *Decoder); 544 545 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 546 uint64_t Address, 547 const void *Decoder); 548 549 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 550 uint64_t Address, const void *Decoder); 551 552 static MCDisassembler *createMipsDisassembler( 553 const Target &T, 554 const MCSubtargetInfo &STI, 555 MCContext &Ctx) { 556 return new MipsDisassembler(STI, Ctx, true); 557 } 558 559 static MCDisassembler *createMipselDisassembler( 560 const Target &T, 561 const MCSubtargetInfo &STI, 562 MCContext &Ctx) { 563 return new MipsDisassembler(STI, Ctx, false); 564 } 565 566 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler() { 567 // Register the disassembler. 568 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 569 createMipsDisassembler); 570 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 571 createMipselDisassembler); 572 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 573 createMipsDisassembler); 574 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 575 createMipselDisassembler); 576 } 577 578 #include "MipsGenDisassemblerTables.inc" 579 580 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 581 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 582 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 583 return *(RegInfo->getRegClass(RC).begin() + RegNo); 584 } 585 586 template <typename InsnType> 587 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 588 const void *Decoder) { 589 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 590 591 // The size of the n field depends on the element size 592 // The register class also depends on this. 593 InsnType tmp = fieldFromInstruction(insn, 17, 5); 594 unsigned NSize = 0; 595 DecodeFN RegDecoder = nullptr; 596 if ((tmp & 0x18) == 0x00) { // INSVE_B 597 NSize = 4; 598 RegDecoder = DecodeMSA128BRegisterClass; 599 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 600 NSize = 3; 601 RegDecoder = DecodeMSA128HRegisterClass; 602 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 603 NSize = 2; 604 RegDecoder = DecodeMSA128WRegisterClass; 605 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 606 NSize = 1; 607 RegDecoder = DecodeMSA128DRegisterClass; 608 } else 609 llvm_unreachable("Invalid encoding"); 610 611 assert(NSize != 0 && RegDecoder != nullptr); 612 613 // $wd 614 tmp = fieldFromInstruction(insn, 6, 5); 615 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 616 return MCDisassembler::Fail; 617 // $wd_in 618 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 619 return MCDisassembler::Fail; 620 // $n 621 tmp = fieldFromInstruction(insn, 16, NSize); 622 MI.addOperand(MCOperand::createImm(tmp)); 623 // $ws 624 tmp = fieldFromInstruction(insn, 11, 5); 625 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 626 return MCDisassembler::Fail; 627 // $n2 628 MI.addOperand(MCOperand::createImm(0)); 629 630 return MCDisassembler::Success; 631 } 632 633 template <typename InsnType> 634 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 635 uint64_t Address, const void *Decoder) { 636 InsnType Rs = fieldFromInstruction(insn, 16, 5); 637 InsnType Imm = fieldFromInstruction(insn, 0, 16); 638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 639 Rs))); 640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 641 Rs))); 642 MI.addOperand(MCOperand::createImm(Imm)); 643 644 return MCDisassembler::Success; 645 } 646 647 template <typename InsnType> 648 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 649 const void *Decoder) { 650 InsnType Rs = fieldFromInstruction(insn, 21, 5); 651 InsnType Imm = fieldFromInstruction(insn, 0, 16); 652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 653 Rs))); 654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 655 Rs))); 656 MI.addOperand(MCOperand::createImm(Imm)); 657 658 return MCDisassembler::Success; 659 } 660 661 template <typename InsnType> 662 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 663 uint64_t Address, 664 const void *Decoder) { 665 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 666 // (otherwise we would have matched the ADDI instruction from the earlier 667 // ISA's instead). 668 // 669 // We have: 670 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 671 // BOVC if rs >= rt 672 // BEQZALC if rs == 0 && rt != 0 673 // BEQC if rs < rt && rs != 0 674 675 InsnType Rs = fieldFromInstruction(insn, 21, 5); 676 InsnType Rt = fieldFromInstruction(insn, 16, 5); 677 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 678 bool HasRs = false; 679 680 if (Rs >= Rt) { 681 MI.setOpcode(Mips::BOVC); 682 HasRs = true; 683 } else if (Rs != 0 && Rs < Rt) { 684 MI.setOpcode(Mips::BEQC); 685 HasRs = true; 686 } else 687 MI.setOpcode(Mips::BEQZALC); 688 689 if (HasRs) 690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 691 Rs))); 692 693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 694 Rt))); 695 MI.addOperand(MCOperand::createImm(Imm)); 696 697 return MCDisassembler::Success; 698 } 699 700 template <typename InsnType> 701 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 702 uint64_t Address, 703 const void *Decoder) { 704 InsnType Rt = fieldFromInstruction(insn, 21, 5); 705 InsnType Rs = fieldFromInstruction(insn, 16, 5); 706 int64_t Imm = 0; 707 708 if (Rs >= Rt) { 709 MI.setOpcode(Mips::BOVC_MMR6); 710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 711 Rt))); 712 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 713 Rs))); 714 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 715 } else if (Rs != 0 && Rs < Rt) { 716 MI.setOpcode(Mips::BEQC_MMR6); 717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 718 Rs))); 719 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 720 Rt))); 721 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 722 } else { 723 MI.setOpcode(Mips::BEQZALC_MMR6); 724 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 725 Rt))); 726 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 727 } 728 729 MI.addOperand(MCOperand::createImm(Imm)); 730 731 return MCDisassembler::Success; 732 } 733 734 template <typename InsnType> 735 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 736 uint64_t Address, 737 const void *Decoder) { 738 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 739 // (otherwise we would have matched the ADDI instruction from the earlier 740 // ISA's instead). 741 // 742 // We have: 743 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 744 // BNVC if rs >= rt 745 // BNEZALC if rs == 0 && rt != 0 746 // BNEC if rs < rt && rs != 0 747 748 InsnType Rs = fieldFromInstruction(insn, 21, 5); 749 InsnType Rt = fieldFromInstruction(insn, 16, 5); 750 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 751 bool HasRs = false; 752 753 if (Rs >= Rt) { 754 MI.setOpcode(Mips::BNVC); 755 HasRs = true; 756 } else if (Rs != 0 && Rs < Rt) { 757 MI.setOpcode(Mips::BNEC); 758 HasRs = true; 759 } else 760 MI.setOpcode(Mips::BNEZALC); 761 762 if (HasRs) 763 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 764 Rs))); 765 766 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 767 Rt))); 768 MI.addOperand(MCOperand::createImm(Imm)); 769 770 return MCDisassembler::Success; 771 } 772 773 template <typename InsnType> 774 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 775 uint64_t Address, 776 const void *Decoder) { 777 InsnType Rt = fieldFromInstruction(insn, 21, 5); 778 InsnType Rs = fieldFromInstruction(insn, 16, 5); 779 int64_t Imm = 0; 780 781 if (Rs >= Rt) { 782 MI.setOpcode(Mips::BNVC_MMR6); 783 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 784 Rt))); 785 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 786 Rs))); 787 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 788 } else if (Rs != 0 && Rs < Rt) { 789 MI.setOpcode(Mips::BNEC_MMR6); 790 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 791 Rs))); 792 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 793 Rt))); 794 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 795 } else { 796 MI.setOpcode(Mips::BNEZALC_MMR6); 797 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 798 Rt))); 799 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 800 } 801 802 MI.addOperand(MCOperand::createImm(Imm)); 803 804 return MCDisassembler::Success; 805 } 806 807 template <typename InsnType> 808 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 809 uint64_t Address, 810 const void *Decoder) { 811 // We have: 812 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 813 // Invalid if rt == 0 814 // BGTZC_MMR6 if rs == 0 && rt != 0 815 // BLTZC_MMR6 if rs == rt && rt != 0 816 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 817 818 InsnType Rt = fieldFromInstruction(insn, 21, 5); 819 InsnType Rs = fieldFromInstruction(insn, 16, 5); 820 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 821 bool HasRs = false; 822 823 if (Rt == 0) 824 return MCDisassembler::Fail; 825 else if (Rs == 0) 826 MI.setOpcode(Mips::BGTZC_MMR6); 827 else if (Rs == Rt) 828 MI.setOpcode(Mips::BLTZC_MMR6); 829 else { 830 MI.setOpcode(Mips::BLTC_MMR6); 831 HasRs = true; 832 } 833 834 if (HasRs) 835 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 836 Rs))); 837 838 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 839 Rt))); 840 841 MI.addOperand(MCOperand::createImm(Imm)); 842 843 return MCDisassembler::Success; 844 } 845 846 template <typename InsnType> 847 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 848 uint64_t Address, 849 const void *Decoder) { 850 // We have: 851 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 852 // Invalid if rt == 0 853 // BLEZC_MMR6 if rs == 0 && rt != 0 854 // BGEZC_MMR6 if rs == rt && rt != 0 855 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 856 857 InsnType Rt = fieldFromInstruction(insn, 21, 5); 858 InsnType Rs = fieldFromInstruction(insn, 16, 5); 859 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 860 bool HasRs = false; 861 862 if (Rt == 0) 863 return MCDisassembler::Fail; 864 else if (Rs == 0) 865 MI.setOpcode(Mips::BLEZC_MMR6); 866 else if (Rs == Rt) 867 MI.setOpcode(Mips::BGEZC_MMR6); 868 else { 869 HasRs = true; 870 MI.setOpcode(Mips::BGEC_MMR6); 871 } 872 873 if (HasRs) 874 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 875 Rs))); 876 877 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 878 Rt))); 879 880 MI.addOperand(MCOperand::createImm(Imm)); 881 882 return MCDisassembler::Success; 883 } 884 885 template <typename InsnType> 886 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 887 uint64_t Address, 888 const void *Decoder) { 889 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 890 // (otherwise we would have matched the BLEZL instruction from the earlier 891 // ISA's instead). 892 // 893 // We have: 894 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 895 // Invalid if rs == 0 896 // BLEZC if rs == 0 && rt != 0 897 // BGEZC if rs == rt && rt != 0 898 // BGEC if rs != rt && rs != 0 && rt != 0 899 900 InsnType Rs = fieldFromInstruction(insn, 21, 5); 901 InsnType Rt = fieldFromInstruction(insn, 16, 5); 902 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 903 bool HasRs = false; 904 905 if (Rt == 0) 906 return MCDisassembler::Fail; 907 else if (Rs == 0) 908 MI.setOpcode(Mips::BLEZC); 909 else if (Rs == Rt) 910 MI.setOpcode(Mips::BGEZC); 911 else { 912 HasRs = true; 913 MI.setOpcode(Mips::BGEC); 914 } 915 916 if (HasRs) 917 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 918 Rs))); 919 920 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 921 Rt))); 922 923 MI.addOperand(MCOperand::createImm(Imm)); 924 925 return MCDisassembler::Success; 926 } 927 928 template <typename InsnType> 929 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 930 uint64_t Address, 931 const void *Decoder) { 932 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 933 // (otherwise we would have matched the BGTZL instruction from the earlier 934 // ISA's instead). 935 // 936 // We have: 937 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 938 // Invalid if rs == 0 939 // BGTZC if rs == 0 && rt != 0 940 // BLTZC if rs == rt && rt != 0 941 // BLTC if rs != rt && rs != 0 && rt != 0 942 943 bool HasRs = false; 944 945 InsnType Rs = fieldFromInstruction(insn, 21, 5); 946 InsnType Rt = fieldFromInstruction(insn, 16, 5); 947 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 948 949 if (Rt == 0) 950 return MCDisassembler::Fail; 951 else if (Rs == 0) 952 MI.setOpcode(Mips::BGTZC); 953 else if (Rs == Rt) 954 MI.setOpcode(Mips::BLTZC); 955 else { 956 MI.setOpcode(Mips::BLTC); 957 HasRs = true; 958 } 959 960 if (HasRs) 961 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 962 Rs))); 963 964 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 965 Rt))); 966 967 MI.addOperand(MCOperand::createImm(Imm)); 968 969 return MCDisassembler::Success; 970 } 971 972 template <typename InsnType> 973 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 974 uint64_t Address, 975 const void *Decoder) { 976 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 977 // (otherwise we would have matched the BGTZ instruction from the earlier 978 // ISA's instead). 979 // 980 // We have: 981 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 982 // BGTZ if rt == 0 983 // BGTZALC if rs == 0 && rt != 0 984 // BLTZALC if rs != 0 && rs == rt 985 // BLTUC if rs != 0 && rs != rt 986 987 InsnType Rs = fieldFromInstruction(insn, 21, 5); 988 InsnType Rt = fieldFromInstruction(insn, 16, 5); 989 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 990 bool HasRs = false; 991 bool HasRt = false; 992 993 if (Rt == 0) { 994 MI.setOpcode(Mips::BGTZ); 995 HasRs = true; 996 } else if (Rs == 0) { 997 MI.setOpcode(Mips::BGTZALC); 998 HasRt = true; 999 } else if (Rs == Rt) { 1000 MI.setOpcode(Mips::BLTZALC); 1001 HasRs = true; 1002 } else { 1003 MI.setOpcode(Mips::BLTUC); 1004 HasRs = true; 1005 HasRt = true; 1006 } 1007 1008 if (HasRs) 1009 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1010 Rs))); 1011 1012 if (HasRt) 1013 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1014 Rt))); 1015 1016 MI.addOperand(MCOperand::createImm(Imm)); 1017 1018 return MCDisassembler::Success; 1019 } 1020 1021 template <typename InsnType> 1022 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1023 uint64_t Address, 1024 const void *Decoder) { 1025 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1026 // (otherwise we would have matched the BLEZL instruction from the earlier 1027 // ISA's instead). 1028 // 1029 // We have: 1030 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1031 // Invalid if rs == 0 1032 // BLEZALC if rs == 0 && rt != 0 1033 // BGEZALC if rs == rt && rt != 0 1034 // BGEUC if rs != rt && rs != 0 && rt != 0 1035 1036 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1037 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1038 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1039 bool HasRs = false; 1040 1041 if (Rt == 0) 1042 return MCDisassembler::Fail; 1043 else if (Rs == 0) 1044 MI.setOpcode(Mips::BLEZALC); 1045 else if (Rs == Rt) 1046 MI.setOpcode(Mips::BGEZALC); 1047 else { 1048 HasRs = true; 1049 MI.setOpcode(Mips::BGEUC); 1050 } 1051 1052 if (HasRs) 1053 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1054 Rs))); 1055 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1056 Rt))); 1057 1058 MI.addOperand(MCOperand::createImm(Imm)); 1059 1060 return MCDisassembler::Success; 1061 } 1062 1063 // Override the generated disassembler to produce DEXT all the time. This is 1064 // for feature / behaviour parity with binutils. 1065 template <typename InsnType> 1066 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1067 const void *Decoder) { 1068 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1069 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1070 unsigned Size = 0; 1071 unsigned Pos = 0; 1072 1073 switch (MI.getOpcode()) { 1074 case Mips::DEXT: 1075 Pos = Lsb; 1076 Size = Msbd + 1; 1077 break; 1078 case Mips::DEXTM: 1079 Pos = Lsb; 1080 Size = Msbd + 1 + 32; 1081 break; 1082 case Mips::DEXTU: 1083 Pos = Lsb + 32; 1084 Size = Msbd + 1; 1085 break; 1086 default: 1087 llvm_unreachable("Unknown DEXT instruction!"); 1088 } 1089 1090 MI.setOpcode(Mips::DEXT); 1091 1092 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1093 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1094 1095 MI.addOperand( 1096 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1097 MI.addOperand( 1098 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1099 MI.addOperand(MCOperand::createImm(Pos)); 1100 MI.addOperand(MCOperand::createImm(Size)); 1101 1102 return MCDisassembler::Success; 1103 } 1104 1105 // Override the generated disassembler to produce DINS all the time. This is 1106 // for feature / behaviour parity with binutils. 1107 template <typename InsnType> 1108 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1109 const void *Decoder) { 1110 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1111 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1112 unsigned Size = 0; 1113 unsigned Pos = 0; 1114 1115 switch (MI.getOpcode()) { 1116 case Mips::DINS: 1117 Pos = Lsb; 1118 Size = Msbd + 1 - Pos; 1119 break; 1120 case Mips::DINSM: 1121 Pos = Lsb; 1122 Size = Msbd + 33 - Pos; 1123 break; 1124 case Mips::DINSU: 1125 Pos = Lsb + 32; 1126 // mbsd = pos + size - 33 1127 // mbsd - pos + 33 = size 1128 Size = Msbd + 33 - Pos; 1129 break; 1130 default: 1131 llvm_unreachable("Unknown DINS instruction!"); 1132 } 1133 1134 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1135 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1136 1137 MI.setOpcode(Mips::DINS); 1138 MI.addOperand( 1139 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1140 MI.addOperand( 1141 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1142 MI.addOperand(MCOperand::createImm(Pos)); 1143 MI.addOperand(MCOperand::createImm(Size)); 1144 1145 return MCDisassembler::Success; 1146 } 1147 1148 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1149 template <typename InsnType> 1150 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1151 const void *Decoder) { 1152 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1153 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1154 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1155 Rt))); 1156 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1157 Rs))); 1158 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1159 Rt))); 1160 return MCDisassembler::Success; 1161 } 1162 1163 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1164 /// according to the given endianness. 1165 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1166 uint64_t &Size, uint32_t &Insn, 1167 bool IsBigEndian) { 1168 // We want to read exactly 2 Bytes of data. 1169 if (Bytes.size() < 2) { 1170 Size = 0; 1171 return MCDisassembler::Fail; 1172 } 1173 1174 if (IsBigEndian) { 1175 Insn = (Bytes[0] << 8) | Bytes[1]; 1176 } else { 1177 Insn = (Bytes[1] << 8) | Bytes[0]; 1178 } 1179 1180 return MCDisassembler::Success; 1181 } 1182 1183 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1184 /// according to the given endianness. 1185 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1186 uint64_t &Size, uint32_t &Insn, 1187 bool IsBigEndian, bool IsMicroMips) { 1188 // We want to read exactly 4 Bytes of data. 1189 if (Bytes.size() < 4) { 1190 Size = 0; 1191 return MCDisassembler::Fail; 1192 } 1193 1194 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1195 // always precede the low 16 bits in the instruction stream (that is, they 1196 // are placed at lower addresses in the instruction stream). 1197 // 1198 // microMIPS byte ordering: 1199 // Big-endian: 0 | 1 | 2 | 3 1200 // Little-endian: 1 | 0 | 3 | 2 1201 1202 if (IsBigEndian) { 1203 // Encoded as a big-endian 32-bit word in the stream. 1204 Insn = 1205 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1206 } else { 1207 if (IsMicroMips) { 1208 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1209 (Bytes[1] << 24); 1210 } else { 1211 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1212 (Bytes[3] << 24); 1213 } 1214 } 1215 1216 return MCDisassembler::Success; 1217 } 1218 1219 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1220 ArrayRef<uint8_t> Bytes, 1221 uint64_t Address, 1222 raw_ostream &CStream) const { 1223 uint32_t Insn; 1224 DecodeStatus Result; 1225 Size = 0; 1226 1227 if (IsMicroMips) { 1228 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1229 if (Result == MCDisassembler::Fail) 1230 return MCDisassembler::Fail; 1231 1232 if (hasMips32r6()) { 1233 LLVM_DEBUG( 1234 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1235 // Calling the auto-generated decoder function for microMIPS32R6 1236 // 16-bit instructions. 1237 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1238 Address, this, STI); 1239 if (Result != MCDisassembler::Fail) { 1240 Size = 2; 1241 return Result; 1242 } 1243 } 1244 1245 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1246 // Calling the auto-generated decoder function for microMIPS 16-bit 1247 // instructions. 1248 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1249 this, STI); 1250 if (Result != MCDisassembler::Fail) { 1251 Size = 2; 1252 return Result; 1253 } 1254 1255 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1256 if (Result == MCDisassembler::Fail) 1257 return MCDisassembler::Fail; 1258 1259 if (hasMips32r6()) { 1260 LLVM_DEBUG( 1261 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1262 // Calling the auto-generated decoder function. 1263 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, 1264 Address, this, STI); 1265 if (Result != MCDisassembler::Fail) { 1266 Size = 4; 1267 return Result; 1268 } 1269 } 1270 1271 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1272 // Calling the auto-generated decoder function. 1273 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1274 this, STI); 1275 if (Result != MCDisassembler::Fail) { 1276 Size = 4; 1277 return Result; 1278 } 1279 1280 if (isFP64()) { 1281 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1282 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1283 Address, this, STI); 1284 if (Result != MCDisassembler::Fail) { 1285 Size = 4; 1286 return Result; 1287 } 1288 } 1289 1290 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1291 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1292 // could form a valid instruction. The two bytes we rejected as an 1293 // instruction could have actually beeen an inline constant pool that is 1294 // unconditionally branched over. 1295 Size = 2; 1296 return MCDisassembler::Fail; 1297 } 1298 1299 // Attempt to read the instruction so that we can attempt to decode it. If 1300 // the buffer is not 4 bytes long, let the higher level logic figure out 1301 // what to do with a size of zero and MCDisassembler::Fail. 1302 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1303 if (Result == MCDisassembler::Fail) 1304 return MCDisassembler::Fail; 1305 1306 // The only instruction size for standard encoded MIPS. 1307 Size = 4; 1308 1309 if (hasCOP3()) { 1310 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1311 Result = 1312 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1313 if (Result != MCDisassembler::Fail) 1314 return Result; 1315 } 1316 1317 if (hasMips32r6() && isGP64()) { 1318 LLVM_DEBUG( 1319 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1320 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1321 Address, this, STI); 1322 if (Result != MCDisassembler::Fail) 1323 return Result; 1324 } 1325 1326 if (hasMips32r6() && isPTR64()) { 1327 LLVM_DEBUG( 1328 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1329 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1330 Address, this, STI); 1331 if (Result != MCDisassembler::Fail) 1332 return Result; 1333 } 1334 1335 if (hasMips32r6()) { 1336 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1337 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1338 Address, this, STI); 1339 if (Result != MCDisassembler::Fail) 1340 return Result; 1341 } 1342 1343 if (hasMips2() && isPTR64()) { 1344 LLVM_DEBUG( 1345 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1346 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1347 Address, this, STI); 1348 if (Result != MCDisassembler::Fail) 1349 return Result; 1350 } 1351 1352 if (hasCnMips()) { 1353 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1354 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1355 Address, this, STI); 1356 if (Result != MCDisassembler::Fail) 1357 return Result; 1358 } 1359 1360 if (hasCnMipsP()) { 1361 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n"); 1362 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, 1363 Address, this, STI); 1364 if (Result != MCDisassembler::Fail) 1365 return Result; 1366 } 1367 1368 if (isGP64()) { 1369 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1370 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1371 Address, this, STI); 1372 if (Result != MCDisassembler::Fail) 1373 return Result; 1374 } 1375 1376 if (isFP64()) { 1377 LLVM_DEBUG( 1378 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1379 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1380 Address, this, STI); 1381 if (Result != MCDisassembler::Fail) 1382 return Result; 1383 } 1384 1385 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1386 // Calling the auto-generated decoder function. 1387 Result = 1388 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1389 if (Result != MCDisassembler::Fail) 1390 return Result; 1391 1392 return MCDisassembler::Fail; 1393 } 1394 1395 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1396 unsigned RegNo, 1397 uint64_t Address, 1398 const void *Decoder) { 1399 return MCDisassembler::Fail; 1400 } 1401 1402 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1403 unsigned RegNo, 1404 uint64_t Address, 1405 const void *Decoder) { 1406 if (RegNo > 31) 1407 return MCDisassembler::Fail; 1408 1409 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1410 Inst.addOperand(MCOperand::createReg(Reg)); 1411 return MCDisassembler::Success; 1412 } 1413 1414 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1415 unsigned RegNo, 1416 uint64_t Address, 1417 const void *Decoder) { 1418 if (RegNo > 7) 1419 return MCDisassembler::Fail; 1420 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1421 Inst.addOperand(MCOperand::createReg(Reg)); 1422 return MCDisassembler::Success; 1423 } 1424 1425 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1426 unsigned RegNo, 1427 uint64_t Address, 1428 const void *Decoder) { 1429 if (RegNo > 7) 1430 return MCDisassembler::Fail; 1431 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1432 Inst.addOperand(MCOperand::createReg(Reg)); 1433 return MCDisassembler::Success; 1434 } 1435 1436 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1437 unsigned RegNo, 1438 uint64_t Address, 1439 const void *Decoder) { 1440 if (RegNo > 7) 1441 return MCDisassembler::Fail; 1442 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1443 Inst.addOperand(MCOperand::createReg(Reg)); 1444 return MCDisassembler::Success; 1445 } 1446 1447 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1448 unsigned RegNo, 1449 uint64_t Address, 1450 const void *Decoder) { 1451 if (RegNo > 31) 1452 return MCDisassembler::Fail; 1453 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1454 Inst.addOperand(MCOperand::createReg(Reg)); 1455 return MCDisassembler::Success; 1456 } 1457 1458 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1459 unsigned RegNo, 1460 uint64_t Address, 1461 const void *Decoder) { 1462 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1463 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1464 1465 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1466 } 1467 1468 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1469 unsigned RegNo, 1470 uint64_t Address, 1471 const void *Decoder) { 1472 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1473 } 1474 1475 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1476 unsigned RegNo, 1477 uint64_t Address, 1478 const void *Decoder) { 1479 if (RegNo > 31) 1480 return MCDisassembler::Fail; 1481 1482 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1483 Inst.addOperand(MCOperand::createReg(Reg)); 1484 return MCDisassembler::Success; 1485 } 1486 1487 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1488 unsigned RegNo, 1489 uint64_t Address, 1490 const void *Decoder) { 1491 if (RegNo > 31) 1492 return MCDisassembler::Fail; 1493 1494 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1495 Inst.addOperand(MCOperand::createReg(Reg)); 1496 return MCDisassembler::Success; 1497 } 1498 1499 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1500 unsigned RegNo, 1501 uint64_t Address, 1502 const void *Decoder) { 1503 if (RegNo > 31) 1504 return MCDisassembler::Fail; 1505 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1506 Inst.addOperand(MCOperand::createReg(Reg)); 1507 return MCDisassembler::Success; 1508 } 1509 1510 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1511 unsigned RegNo, 1512 uint64_t Address, 1513 const void *Decoder) { 1514 if (RegNo > 7) 1515 return MCDisassembler::Fail; 1516 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1517 Inst.addOperand(MCOperand::createReg(Reg)); 1518 return MCDisassembler::Success; 1519 } 1520 1521 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1522 uint64_t Address, 1523 const void *Decoder) { 1524 if (RegNo > 31) 1525 return MCDisassembler::Fail; 1526 1527 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1528 Inst.addOperand(MCOperand::createReg(Reg)); 1529 return MCDisassembler::Success; 1530 } 1531 1532 static DecodeStatus DecodeMem(MCInst &Inst, 1533 unsigned Insn, 1534 uint64_t Address, 1535 const void *Decoder) { 1536 int Offset = SignExtend32<16>(Insn & 0xffff); 1537 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1538 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1539 1540 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1541 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1542 1543 if (Inst.getOpcode() == Mips::SC || 1544 Inst.getOpcode() == Mips::SCD) 1545 Inst.addOperand(MCOperand::createReg(Reg)); 1546 1547 Inst.addOperand(MCOperand::createReg(Reg)); 1548 Inst.addOperand(MCOperand::createReg(Base)); 1549 Inst.addOperand(MCOperand::createImm(Offset)); 1550 1551 return MCDisassembler::Success; 1552 } 1553 1554 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1555 unsigned Insn, 1556 uint64_t Address, 1557 const void *Decoder) { 1558 int Offset = SignExtend32<9>(Insn >> 7); 1559 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1560 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1561 1562 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1563 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1564 1565 if (Inst.getOpcode() == Mips::SCE) 1566 Inst.addOperand(MCOperand::createReg(Reg)); 1567 1568 Inst.addOperand(MCOperand::createReg(Reg)); 1569 Inst.addOperand(MCOperand::createReg(Base)); 1570 Inst.addOperand(MCOperand::createImm(Offset)); 1571 1572 return MCDisassembler::Success; 1573 } 1574 1575 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1576 unsigned Insn, 1577 uint64_t Address, 1578 const void *Decoder) { 1579 int Offset = SignExtend32<16>(Insn & 0xffff); 1580 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1581 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1582 1583 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1584 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1585 1586 Inst.addOperand(MCOperand::createReg(Reg)); 1587 Inst.addOperand(MCOperand::createReg(Base)); 1588 Inst.addOperand(MCOperand::createImm(Offset)); 1589 1590 return MCDisassembler::Success; 1591 } 1592 1593 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1594 unsigned Insn, 1595 uint64_t Address, 1596 const void *Decoder) { 1597 int Offset = SignExtend32<16>(Insn & 0xffff); 1598 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1599 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1600 1601 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1602 1603 Inst.addOperand(MCOperand::createReg(Base)); 1604 Inst.addOperand(MCOperand::createImm(Offset)); 1605 Inst.addOperand(MCOperand::createImm(Hint)); 1606 1607 return MCDisassembler::Success; 1608 } 1609 1610 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1611 unsigned Insn, 1612 uint64_t Address, 1613 const void *Decoder) { 1614 int Offset = SignExtend32<12>(Insn & 0xfff); 1615 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1616 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1617 1618 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1619 1620 Inst.addOperand(MCOperand::createReg(Base)); 1621 Inst.addOperand(MCOperand::createImm(Offset)); 1622 Inst.addOperand(MCOperand::createImm(Hint)); 1623 1624 return MCDisassembler::Success; 1625 } 1626 1627 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1628 unsigned Insn, 1629 uint64_t Address, 1630 const void *Decoder) { 1631 int Offset = SignExtend32<9>(Insn & 0x1ff); 1632 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1633 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1634 1635 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1636 1637 Inst.addOperand(MCOperand::createReg(Base)); 1638 Inst.addOperand(MCOperand::createImm(Offset)); 1639 Inst.addOperand(MCOperand::createImm(Hint)); 1640 1641 return MCDisassembler::Success; 1642 } 1643 1644 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1645 unsigned Insn, 1646 uint64_t Address, 1647 const void *Decoder) { 1648 int Offset = SignExtend32<9>(Insn >> 7); 1649 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1650 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1651 1652 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1653 1654 Inst.addOperand(MCOperand::createReg(Base)); 1655 Inst.addOperand(MCOperand::createImm(Offset)); 1656 Inst.addOperand(MCOperand::createImm(Hint)); 1657 1658 return MCDisassembler::Success; 1659 } 1660 1661 static DecodeStatus DecodeSyncI(MCInst &Inst, 1662 unsigned Insn, 1663 uint64_t Address, 1664 const void *Decoder) { 1665 int Offset = SignExtend32<16>(Insn & 0xffff); 1666 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1667 1668 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1669 1670 Inst.addOperand(MCOperand::createReg(Base)); 1671 Inst.addOperand(MCOperand::createImm(Offset)); 1672 1673 return MCDisassembler::Success; 1674 } 1675 1676 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1677 uint64_t Address, const void *Decoder) { 1678 int Offset = SignExtend32<16>(Insn & 0xffff); 1679 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1680 1681 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1682 1683 Inst.addOperand(MCOperand::createReg(Base)); 1684 Inst.addOperand(MCOperand::createImm(Offset)); 1685 1686 return MCDisassembler::Success; 1687 } 1688 1689 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1690 unsigned Insn, 1691 uint64_t Address, 1692 const void *Decoder) { 1693 int Immediate = SignExtend32<16>(Insn & 0xffff); 1694 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1695 1696 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1697 1698 Inst.addOperand(MCOperand::createReg(Base)); 1699 Inst.addOperand(MCOperand::createImm(Immediate)); 1700 1701 return MCDisassembler::Success; 1702 } 1703 1704 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1705 uint64_t Address, const void *Decoder) { 1706 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1707 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1708 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1709 1710 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1711 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1712 1713 Inst.addOperand(MCOperand::createReg(Reg)); 1714 Inst.addOperand(MCOperand::createReg(Base)); 1715 1716 // The immediate field of an LD/ST instruction is scaled which means it must 1717 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1718 // data format. 1719 // .b - 1 byte 1720 // .h - 2 bytes 1721 // .w - 4 bytes 1722 // .d - 8 bytes 1723 switch(Inst.getOpcode()) 1724 { 1725 default: 1726 assert(false && "Unexpected instruction"); 1727 return MCDisassembler::Fail; 1728 break; 1729 case Mips::LD_B: 1730 case Mips::ST_B: 1731 Inst.addOperand(MCOperand::createImm(Offset)); 1732 break; 1733 case Mips::LD_H: 1734 case Mips::ST_H: 1735 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1736 break; 1737 case Mips::LD_W: 1738 case Mips::ST_W: 1739 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1740 break; 1741 case Mips::LD_D: 1742 case Mips::ST_D: 1743 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1744 break; 1745 } 1746 1747 return MCDisassembler::Success; 1748 } 1749 1750 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1751 unsigned Insn, 1752 uint64_t Address, 1753 const void *Decoder) { 1754 unsigned Offset = Insn & 0xf; 1755 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1756 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1757 1758 switch (Inst.getOpcode()) { 1759 case Mips::LBU16_MM: 1760 case Mips::LHU16_MM: 1761 case Mips::LW16_MM: 1762 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1763 == MCDisassembler::Fail) 1764 return MCDisassembler::Fail; 1765 break; 1766 case Mips::SB16_MM: 1767 case Mips::SB16_MMR6: 1768 case Mips::SH16_MM: 1769 case Mips::SH16_MMR6: 1770 case Mips::SW16_MM: 1771 case Mips::SW16_MMR6: 1772 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1773 == MCDisassembler::Fail) 1774 return MCDisassembler::Fail; 1775 break; 1776 } 1777 1778 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1779 == MCDisassembler::Fail) 1780 return MCDisassembler::Fail; 1781 1782 switch (Inst.getOpcode()) { 1783 case Mips::LBU16_MM: 1784 if (Offset == 0xf) 1785 Inst.addOperand(MCOperand::createImm(-1)); 1786 else 1787 Inst.addOperand(MCOperand::createImm(Offset)); 1788 break; 1789 case Mips::SB16_MM: 1790 case Mips::SB16_MMR6: 1791 Inst.addOperand(MCOperand::createImm(Offset)); 1792 break; 1793 case Mips::LHU16_MM: 1794 case Mips::SH16_MM: 1795 case Mips::SH16_MMR6: 1796 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1797 break; 1798 case Mips::LW16_MM: 1799 case Mips::SW16_MM: 1800 case Mips::SW16_MMR6: 1801 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1802 break; 1803 } 1804 1805 return MCDisassembler::Success; 1806 } 1807 1808 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1809 unsigned Insn, 1810 uint64_t Address, 1811 const void *Decoder) { 1812 unsigned Offset = Insn & 0x1F; 1813 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1814 1815 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1816 1817 Inst.addOperand(MCOperand::createReg(Reg)); 1818 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1819 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1820 1821 return MCDisassembler::Success; 1822 } 1823 1824 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1825 unsigned Insn, 1826 uint64_t Address, 1827 const void *Decoder) { 1828 unsigned Offset = Insn & 0x7F; 1829 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1830 1831 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1832 1833 Inst.addOperand(MCOperand::createReg(Reg)); 1834 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1835 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1836 1837 return MCDisassembler::Success; 1838 } 1839 1840 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1841 unsigned Insn, 1842 uint64_t Address, 1843 const void *Decoder) { 1844 int Offset; 1845 switch (Inst.getOpcode()) { 1846 case Mips::LWM16_MMR6: 1847 case Mips::SWM16_MMR6: 1848 Offset = fieldFromInstruction(Insn, 4, 4); 1849 break; 1850 default: 1851 Offset = SignExtend32<4>(Insn & 0xf); 1852 break; 1853 } 1854 1855 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1856 == MCDisassembler::Fail) 1857 return MCDisassembler::Fail; 1858 1859 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1860 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1861 1862 return MCDisassembler::Success; 1863 } 1864 1865 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1866 unsigned Insn, 1867 uint64_t Address, 1868 const void *Decoder) { 1869 int Offset = SignExtend32<9>(Insn & 0x1ff); 1870 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1871 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1872 1873 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1874 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1875 1876 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) 1877 Inst.addOperand(MCOperand::createReg(Reg)); 1878 1879 Inst.addOperand(MCOperand::createReg(Reg)); 1880 Inst.addOperand(MCOperand::createReg(Base)); 1881 Inst.addOperand(MCOperand::createImm(Offset)); 1882 1883 return MCDisassembler::Success; 1884 } 1885 1886 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1887 unsigned Insn, 1888 uint64_t Address, 1889 const void *Decoder) { 1890 int Offset = SignExtend32<12>(Insn & 0x0fff); 1891 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1892 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1893 1894 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1895 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1896 1897 switch (Inst.getOpcode()) { 1898 case Mips::SWM32_MM: 1899 case Mips::LWM32_MM: 1900 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1901 == MCDisassembler::Fail) 1902 return MCDisassembler::Fail; 1903 Inst.addOperand(MCOperand::createReg(Base)); 1904 Inst.addOperand(MCOperand::createImm(Offset)); 1905 break; 1906 case Mips::SC_MM: 1907 Inst.addOperand(MCOperand::createReg(Reg)); 1908 LLVM_FALLTHROUGH; 1909 default: 1910 Inst.addOperand(MCOperand::createReg(Reg)); 1911 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1912 Inst.addOperand(MCOperand::createReg(Reg+1)); 1913 1914 Inst.addOperand(MCOperand::createReg(Base)); 1915 Inst.addOperand(MCOperand::createImm(Offset)); 1916 } 1917 1918 return MCDisassembler::Success; 1919 } 1920 1921 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1922 unsigned Insn, 1923 uint64_t Address, 1924 const void *Decoder) { 1925 int Offset = SignExtend32<16>(Insn & 0xffff); 1926 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1927 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1928 1929 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1930 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1931 1932 Inst.addOperand(MCOperand::createReg(Reg)); 1933 Inst.addOperand(MCOperand::createReg(Base)); 1934 Inst.addOperand(MCOperand::createImm(Offset)); 1935 1936 return MCDisassembler::Success; 1937 } 1938 1939 static DecodeStatus DecodeFMem(MCInst &Inst, 1940 unsigned Insn, 1941 uint64_t Address, 1942 const void *Decoder) { 1943 int Offset = SignExtend32<16>(Insn & 0xffff); 1944 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1945 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1946 1947 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1948 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1949 1950 Inst.addOperand(MCOperand::createReg(Reg)); 1951 Inst.addOperand(MCOperand::createReg(Base)); 1952 Inst.addOperand(MCOperand::createImm(Offset)); 1953 1954 return MCDisassembler::Success; 1955 } 1956 1957 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1958 uint64_t Address, const void *Decoder) { 1959 // This function is the same as DecodeFMem but with the Reg and Base fields 1960 // swapped according to microMIPS spec. 1961 int Offset = SignExtend32<16>(Insn & 0xffff); 1962 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1963 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1964 1965 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1966 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1967 1968 Inst.addOperand(MCOperand::createReg(Reg)); 1969 Inst.addOperand(MCOperand::createReg(Base)); 1970 Inst.addOperand(MCOperand::createImm(Offset)); 1971 1972 return MCDisassembler::Success; 1973 } 1974 1975 static DecodeStatus DecodeFMem2(MCInst &Inst, 1976 unsigned Insn, 1977 uint64_t Address, 1978 const void *Decoder) { 1979 int Offset = SignExtend32<16>(Insn & 0xffff); 1980 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1981 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1982 1983 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1984 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1985 1986 Inst.addOperand(MCOperand::createReg(Reg)); 1987 Inst.addOperand(MCOperand::createReg(Base)); 1988 Inst.addOperand(MCOperand::createImm(Offset)); 1989 1990 return MCDisassembler::Success; 1991 } 1992 1993 static DecodeStatus DecodeFMem3(MCInst &Inst, 1994 unsigned Insn, 1995 uint64_t Address, 1996 const void *Decoder) { 1997 int Offset = SignExtend32<16>(Insn & 0xffff); 1998 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1999 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2000 2001 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 2002 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2003 2004 Inst.addOperand(MCOperand::createReg(Reg)); 2005 Inst.addOperand(MCOperand::createReg(Base)); 2006 Inst.addOperand(MCOperand::createImm(Offset)); 2007 2008 return MCDisassembler::Success; 2009 } 2010 2011 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2012 unsigned Insn, 2013 uint64_t Address, 2014 const void *Decoder) { 2015 int Offset = SignExtend32<11>(Insn & 0x07ff); 2016 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2017 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2018 2019 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2020 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2021 2022 Inst.addOperand(MCOperand::createReg(Reg)); 2023 Inst.addOperand(MCOperand::createReg(Base)); 2024 Inst.addOperand(MCOperand::createImm(Offset)); 2025 2026 return MCDisassembler::Success; 2027 } 2028 2029 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2030 uint64_t Address, const void *Decoder) { 2031 int Offset = SignExtend32<11>(Insn & 0x07ff); 2032 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2033 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2034 2035 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2036 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2037 2038 Inst.addOperand(MCOperand::createReg(Reg)); 2039 Inst.addOperand(MCOperand::createReg(Base)); 2040 Inst.addOperand(MCOperand::createImm(Offset)); 2041 2042 return MCDisassembler::Success; 2043 } 2044 2045 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2046 unsigned Insn, 2047 uint64_t Address, 2048 const void *Decoder) { 2049 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2050 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2051 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2052 2053 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2054 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2055 2056 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2057 Inst.addOperand(MCOperand::createReg(Rt)); 2058 } 2059 2060 Inst.addOperand(MCOperand::createReg(Rt)); 2061 Inst.addOperand(MCOperand::createReg(Base)); 2062 Inst.addOperand(MCOperand::createImm(Offset)); 2063 2064 return MCDisassembler::Success; 2065 } 2066 2067 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2068 unsigned RegNo, 2069 uint64_t Address, 2070 const void *Decoder) { 2071 // Currently only hardware register 29 is supported. 2072 if (RegNo != 29) 2073 return MCDisassembler::Fail; 2074 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2075 return MCDisassembler::Success; 2076 } 2077 2078 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2079 unsigned RegNo, 2080 uint64_t Address, 2081 const void *Decoder) { 2082 if (RegNo > 30 || RegNo %2) 2083 return MCDisassembler::Fail; 2084 2085 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2086 Inst.addOperand(MCOperand::createReg(Reg)); 2087 return MCDisassembler::Success; 2088 } 2089 2090 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2091 unsigned RegNo, 2092 uint64_t Address, 2093 const void *Decoder) { 2094 if (RegNo >= 4) 2095 return MCDisassembler::Fail; 2096 2097 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2098 Inst.addOperand(MCOperand::createReg(Reg)); 2099 return MCDisassembler::Success; 2100 } 2101 2102 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2103 unsigned RegNo, 2104 uint64_t Address, 2105 const void *Decoder) { 2106 if (RegNo >= 4) 2107 return MCDisassembler::Fail; 2108 2109 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2110 Inst.addOperand(MCOperand::createReg(Reg)); 2111 return MCDisassembler::Success; 2112 } 2113 2114 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2115 unsigned RegNo, 2116 uint64_t Address, 2117 const void *Decoder) { 2118 if (RegNo >= 4) 2119 return MCDisassembler::Fail; 2120 2121 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2122 Inst.addOperand(MCOperand::createReg(Reg)); 2123 return MCDisassembler::Success; 2124 } 2125 2126 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2127 unsigned RegNo, 2128 uint64_t Address, 2129 const void *Decoder) { 2130 if (RegNo > 31) 2131 return MCDisassembler::Fail; 2132 2133 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2134 Inst.addOperand(MCOperand::createReg(Reg)); 2135 return MCDisassembler::Success; 2136 } 2137 2138 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2139 unsigned RegNo, 2140 uint64_t Address, 2141 const void *Decoder) { 2142 if (RegNo > 31) 2143 return MCDisassembler::Fail; 2144 2145 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2146 Inst.addOperand(MCOperand::createReg(Reg)); 2147 return MCDisassembler::Success; 2148 } 2149 2150 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2151 unsigned RegNo, 2152 uint64_t Address, 2153 const void *Decoder) { 2154 if (RegNo > 31) 2155 return MCDisassembler::Fail; 2156 2157 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2158 Inst.addOperand(MCOperand::createReg(Reg)); 2159 return MCDisassembler::Success; 2160 } 2161 2162 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2163 unsigned RegNo, 2164 uint64_t Address, 2165 const void *Decoder) { 2166 if (RegNo > 31) 2167 return MCDisassembler::Fail; 2168 2169 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2170 Inst.addOperand(MCOperand::createReg(Reg)); 2171 return MCDisassembler::Success; 2172 } 2173 2174 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2175 unsigned RegNo, 2176 uint64_t Address, 2177 const void *Decoder) { 2178 if (RegNo > 7) 2179 return MCDisassembler::Fail; 2180 2181 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2182 Inst.addOperand(MCOperand::createReg(Reg)); 2183 return MCDisassembler::Success; 2184 } 2185 2186 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2187 unsigned RegNo, 2188 uint64_t Address, 2189 const void *Decoder) { 2190 if (RegNo > 31) 2191 return MCDisassembler::Fail; 2192 2193 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2194 Inst.addOperand(MCOperand::createReg(Reg)); 2195 return MCDisassembler::Success; 2196 } 2197 2198 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2199 unsigned RegNo, 2200 uint64_t Address, 2201 const void *Decoder) { 2202 if (RegNo > 31) 2203 return MCDisassembler::Fail; 2204 2205 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2206 Inst.addOperand(MCOperand::createReg(Reg)); 2207 return MCDisassembler::Success; 2208 } 2209 2210 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2211 unsigned Offset, 2212 uint64_t Address, 2213 const void *Decoder) { 2214 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2215 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2216 return MCDisassembler::Success; 2217 } 2218 2219 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2220 unsigned Offset, 2221 uint64_t Address, 2222 const void *Decoder) { 2223 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2224 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2225 return MCDisassembler::Success; 2226 } 2227 2228 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2229 unsigned Insn, 2230 uint64_t Address, 2231 const void *Decoder) { 2232 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2233 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2234 return MCDisassembler::Success; 2235 } 2236 2237 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2238 unsigned Offset, 2239 uint64_t Address, 2240 const void *Decoder) { 2241 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2242 2243 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2244 return MCDisassembler::Success; 2245 } 2246 2247 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2248 unsigned Offset, 2249 uint64_t Address, 2250 const void *Decoder) { 2251 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2252 2253 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2254 return MCDisassembler::Success; 2255 } 2256 2257 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2258 unsigned Offset, 2259 uint64_t Address, 2260 const void *Decoder) { 2261 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2262 2263 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2264 return MCDisassembler::Success; 2265 } 2266 2267 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2268 unsigned Offset, 2269 uint64_t Address, 2270 const void *Decoder) { 2271 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2272 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2273 return MCDisassembler::Success; 2274 } 2275 2276 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2277 unsigned Offset, 2278 uint64_t Address, 2279 const void *Decoder) { 2280 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2281 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2282 return MCDisassembler::Success; 2283 } 2284 2285 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2286 unsigned Offset, 2287 uint64_t Address, 2288 const void *Decoder) { 2289 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2290 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2291 return MCDisassembler::Success; 2292 } 2293 2294 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2295 unsigned Offset, 2296 uint64_t Address, 2297 const void *Decoder) { 2298 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2299 2300 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2301 return MCDisassembler::Success; 2302 } 2303 2304 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2305 unsigned Insn, 2306 uint64_t Address, 2307 const void *Decoder) { 2308 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2309 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2310 return MCDisassembler::Success; 2311 } 2312 2313 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 2314 unsigned Insn, 2315 uint64_t Address, 2316 const void *Decoder) { 2317 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2318 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2319 return MCDisassembler::Success; 2320 } 2321 2322 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2323 unsigned Value, 2324 uint64_t Address, 2325 const void *Decoder) { 2326 if (Value == 0) 2327 Inst.addOperand(MCOperand::createImm(1)); 2328 else if (Value == 0x7) 2329 Inst.addOperand(MCOperand::createImm(-1)); 2330 else 2331 Inst.addOperand(MCOperand::createImm(Value << 2)); 2332 return MCDisassembler::Success; 2333 } 2334 2335 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2336 unsigned Value, 2337 uint64_t Address, 2338 const void *Decoder) { 2339 if (Value == 0x7F) 2340 Inst.addOperand(MCOperand::createImm(-1)); 2341 else 2342 Inst.addOperand(MCOperand::createImm(Value)); 2343 return MCDisassembler::Success; 2344 } 2345 2346 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2347 unsigned Value, 2348 uint64_t Address, 2349 const void *Decoder) { 2350 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2351 return MCDisassembler::Success; 2352 } 2353 2354 template <unsigned Bits, int Offset, int Scale> 2355 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2356 uint64_t Address, 2357 const void *Decoder) { 2358 Value &= ((1 << Bits) - 1); 2359 Value *= Scale; 2360 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2361 return MCDisassembler::Success; 2362 } 2363 2364 template <unsigned Bits, int Offset, int ScaleBy> 2365 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2366 uint64_t Address, 2367 const void *Decoder) { 2368 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2369 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2370 return MCDisassembler::Success; 2371 } 2372 2373 static DecodeStatus DecodeInsSize(MCInst &Inst, 2374 unsigned Insn, 2375 uint64_t Address, 2376 const void *Decoder) { 2377 // First we need to grab the pos(lsb) from MCInst. 2378 // This function only handles the 32 bit variants of ins, as dins 2379 // variants are handled differently. 2380 int Pos = Inst.getOperand(2).getImm(); 2381 int Size = (int) Insn - Pos + 1; 2382 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2383 return MCDisassembler::Success; 2384 } 2385 2386 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2387 uint64_t Address, const void *Decoder) { 2388 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2389 return MCDisassembler::Success; 2390 } 2391 2392 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2393 uint64_t Address, const void *Decoder) { 2394 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2395 return MCDisassembler::Success; 2396 } 2397 2398 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2399 uint64_t Address, const void *Decoder) { 2400 int32_t DecodedValue; 2401 switch (Insn) { 2402 case 0: DecodedValue = 256; break; 2403 case 1: DecodedValue = 257; break; 2404 case 510: DecodedValue = -258; break; 2405 case 511: DecodedValue = -257; break; 2406 default: DecodedValue = SignExtend32<9>(Insn); break; 2407 } 2408 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2409 return MCDisassembler::Success; 2410 } 2411 2412 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2413 uint64_t Address, const void *Decoder) { 2414 // Insn must be >= 0, since it is unsigned that condition is always true. 2415 assert(Insn < 16); 2416 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2417 255, 32768, 65535}; 2418 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2419 return MCDisassembler::Success; 2420 } 2421 2422 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2423 unsigned Insn, 2424 uint64_t Address, 2425 const void *Decoder) { 2426 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2427 Mips::S6, Mips::S7, Mips::FP}; 2428 unsigned RegNum; 2429 2430 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2431 2432 // Empty register lists are not allowed. 2433 if (RegLst == 0) 2434 return MCDisassembler::Fail; 2435 2436 RegNum = RegLst & 0xf; 2437 2438 // RegLst values 10-15, and 26-31 are reserved. 2439 if (RegNum > 9) 2440 return MCDisassembler::Fail; 2441 2442 for (unsigned i = 0; i < RegNum; i++) 2443 Inst.addOperand(MCOperand::createReg(Regs[i])); 2444 2445 if (RegLst & 0x10) 2446 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2447 2448 return MCDisassembler::Success; 2449 } 2450 2451 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2452 uint64_t Address, 2453 const void *Decoder) { 2454 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2455 unsigned RegLst; 2456 switch(Inst.getOpcode()) { 2457 default: 2458 RegLst = fieldFromInstruction(Insn, 4, 2); 2459 break; 2460 case Mips::LWM16_MMR6: 2461 case Mips::SWM16_MMR6: 2462 RegLst = fieldFromInstruction(Insn, 8, 2); 2463 break; 2464 } 2465 unsigned RegNum = RegLst & 0x3; 2466 2467 for (unsigned i = 0; i <= RegNum; i++) 2468 Inst.addOperand(MCOperand::createReg(Regs[i])); 2469 2470 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2471 2472 return MCDisassembler::Success; 2473 } 2474 2475 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 2476 uint64_t Address, 2477 const void *Decoder) { 2478 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2479 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == 2480 MCDisassembler::Fail) 2481 return MCDisassembler::Fail; 2482 2483 unsigned RegRs; 2484 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) 2485 RegRs = fieldFromInstruction(Insn, 0, 2) | 2486 (fieldFromInstruction(Insn, 3, 1) << 2); 2487 else 2488 RegRs = fieldFromInstruction(Insn, 1, 3); 2489 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == 2490 MCDisassembler::Fail) 2491 return MCDisassembler::Fail; 2492 2493 unsigned RegRt = fieldFromInstruction(Insn, 4, 3); 2494 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == 2495 MCDisassembler::Fail) 2496 return MCDisassembler::Fail; 2497 2498 return MCDisassembler::Success; 2499 } 2500 2501 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2502 uint64_t Address, const void *Decoder) { 2503 switch (RegPair) { 2504 default: 2505 return MCDisassembler::Fail; 2506 case 0: 2507 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2508 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2509 break; 2510 case 1: 2511 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2512 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2513 break; 2514 case 2: 2515 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2516 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2517 break; 2518 case 3: 2519 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2520 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2521 break; 2522 case 4: 2523 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2524 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2525 break; 2526 case 5: 2527 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2528 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2529 break; 2530 case 6: 2531 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2532 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2533 break; 2534 case 7: 2535 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2536 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2537 break; 2538 } 2539 2540 return MCDisassembler::Success; 2541 } 2542 2543 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2544 uint64_t Address, const void *Decoder) { 2545 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2546 return MCDisassembler::Success; 2547 } 2548 2549 template <typename InsnType> 2550 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2551 uint64_t Address, 2552 const void *Decoder) { 2553 // We have: 2554 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2555 // Invalid if rt == 0 2556 // BGTZALC_MMR6 if rs == 0 && rt != 0 2557 // BLTZALC_MMR6 if rs != 0 && rs == rt 2558 // BLTUC_MMR6 if rs != 0 && rs != rt 2559 2560 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2561 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2562 InsnType Imm = 0; 2563 bool HasRs = false; 2564 bool HasRt = false; 2565 2566 if (Rt == 0) 2567 return MCDisassembler::Fail; 2568 else if (Rs == 0) { 2569 MI.setOpcode(Mips::BGTZALC_MMR6); 2570 HasRt = true; 2571 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2572 } 2573 else if (Rs == Rt) { 2574 MI.setOpcode(Mips::BLTZALC_MMR6); 2575 HasRs = true; 2576 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2577 } 2578 else { 2579 MI.setOpcode(Mips::BLTUC_MMR6); 2580 HasRs = true; 2581 HasRt = true; 2582 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2583 } 2584 2585 if (HasRs) 2586 MI.addOperand( 2587 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2588 2589 if (HasRt) 2590 MI.addOperand( 2591 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2592 2593 MI.addOperand(MCOperand::createImm(Imm)); 2594 2595 return MCDisassembler::Success; 2596 } 2597 2598 template <typename InsnType> 2599 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2600 uint64_t Address, 2601 const void *Decoder) { 2602 // We have: 2603 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2604 // Invalid if rt == 0 2605 // BLEZALC_MMR6 if rs == 0 && rt != 0 2606 // BGEZALC_MMR6 if rs == rt && rt != 0 2607 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2608 2609 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2610 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2611 InsnType Imm = 0; 2612 bool HasRs = false; 2613 2614 if (Rt == 0) 2615 return MCDisassembler::Fail; 2616 else if (Rs == 0) { 2617 MI.setOpcode(Mips::BLEZALC_MMR6); 2618 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2619 } 2620 else if (Rs == Rt) { 2621 MI.setOpcode(Mips::BGEZALC_MMR6); 2622 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2623 } 2624 else { 2625 HasRs = true; 2626 MI.setOpcode(Mips::BGEUC_MMR6); 2627 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2628 } 2629 2630 if (HasRs) 2631 MI.addOperand( 2632 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2633 MI.addOperand( 2634 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2635 2636 MI.addOperand(MCOperand::createImm(Imm)); 2637 2638 return MCDisassembler::Success; 2639 } 2640
Indexes created Tue Jun 09 00:24:00 UTC 2026