HomeSort by: relevance | last modified time | path
    Searched refs:Dst0Reg (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 2098 Register Dst0Reg = MI.getOperand(0).getReg();
2099 LLT Dst0Ty = MRI.getType(Dst0Reg);
2102 Builder.buildCast(Dst0Reg, MIB);
2104 Builder.buildTrunc(Dst0Reg, SrcReg);
2112 Register Dst0Reg = MI.getOperand(0).getReg();
2113 LLT Dst0Ty = MRI.getType(Dst0Reg);
2139 Register Dst0Reg = MI.getOperand(0).getReg();
2147 LLT Dst0Ty = MRI.getType(Dst0Reg);
2153 Builder.buildZExt(Dst0Reg, ZExtSrcReg);
2157 replaceRegWith(MRI, Dst0Reg, ZExtSrcReg)
    [all...]
LegalizerHelper.cpp 1504 Register Dst0Reg = MI.getOperand(0).getReg();
1505 LLT DstTy = MRI.getType(Dst0Reg);
1534 MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
6194 Register Dst0Reg = MI.getOperand(0).getReg();
6195 LLT DstTy = MRI.getType(Dst0Reg);
6206 MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 406 Register Dst0Reg = I.getOperand(0).getReg();
434 BuildMI(*BB, &I, DL, TII.get(HasCarryIn ? CarryOpc : NoCarryOpc), Dst0Reg)
443 if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, *MRI) ||

Completed in 74 milliseconds