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    Searched refs:DstBank (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 150 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);
151 assert(DstBank != &AMDGPU::VCCRegBank);
1147 const RegisterBank *DstBank =
1149 if (DstBank == &AMDGPU::SGPRRegBank) {
1547 const RegisterBank *DstBank =
1549 if (DstBank == &AMDGPU::VGPRRegBank) {
1921 const RegisterBank &DstBank =
1927 (DstBank == AMDGPU::SGPRRegBank &&
1962 MRI.setRegBank(S->getOperand(N).getReg(), DstBank);
1971 MRI.setRegBank(DstReg, DstBank);
    [all...]
AMDGPUInstructionSelector.cpp 514 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
517 TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI);
599 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI);
600 if (DstBank->getID() != AMDGPU::SGPRRegBankID)
724 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
726 TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI);
1132 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
1134 TRI.getRegClassForSizeOnBank(32, *DstBank, *MRI);
1138 const bool IsVALU = DstBank->getID() == AMDGPU::VGPRRegBankID;
1999 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 771 static bool isValidCopy(const MachineInstr &I, const RegisterBank &DstBank,
793 assert((DstSize <= 64 || DstBank.getID() == AArch64::FPRRegBankID) &&

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