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    Searched refs:DstRB (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64RegisterBankInfo.cpp 622 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
624 if (!DstRB)
625 DstRB = SrcRB;
627 SrcRB = DstRB;
630 assert(DstRB && SrcRB && "Both RegBank were nullptr");
633 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size),
634 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
647 const RegisterBank &DstRB =
652 DefaultMappingID, copyCost(DstRB, SrcRB, Size),
653 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size)
    [all...]
AArch64InstructionSelector.cpp 263 const RegisterBank &DstRB, LLT ScalarTy,
2478 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
2479 assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!");
2492 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB);
2819 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
2822 if (DstRB.getID() != SrcRB.getID()) {
2828 if (DstRB.getID() == AArch64::GPRRegBankID) {
2830 getRegClassForTypeOnBank(DstTy, DstRB, RBI);
2862 } else if (DstRB.getID() == AArch64::FPRRegBankID) {
2871 DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 283 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
284 if (DstRB->getID() != AMDGPU::SGPRRegBankID &&
285 DstRB->getID() != AMDGPU::VCCRegBankID)
288 bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID &&
310 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
311 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID;
1159 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
1160 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ?
1840 const RegisterBank *DstRB;
1844 DstRB = SrcRB
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 719 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
722 if (DstRB.getID() != SrcRB.getID()) {
728 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
740 if (DstRB.getID() != X86::GPRRegBankID)
848 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
851 assert(DstRB.getID() == SrcRB.getID() &&
857 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
866 if (DstRB.getID() != X86::GPRRegBankID)

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