Searched refs:JH7110_STGCLK_PCIE1_AXI_MST0 (Results 1 - 3 of 3) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h240 #define JH7110_STGCLK_PCIE1_AXI_MST0 11 macro
/src/sys/arch/riscv/starfive/
H A Djh7110_clkc.c276 #define JH7110_STGCLK_PCIE1_AXI_MST0 11 macro
719 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", "stg_axiahb"),
/src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1290 <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,

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